參數(shù)資料
型號(hào)： HPC
文件頁(yè)數(shù)： 24/30頁(yè)
文件大?。?/td> 361K
代理商： HPC
Address Decode
Address decode is a common function required when ac-
cessing memory. To aid in this function a group of 7 memory
access decode signals are available. The 64k memory map
has been divided into eleven uneven blocks. A decode sig-
nal points to a respective block of user space. The remain-
ing four blocks are accessed by internal register or RAM
memory. The latched address select bits may be used with
the required number of LSBs to decrease the amount of
circuitry necessary to decode a unique address.
Figure 19 shows the signal decode mapping. The select bit
SLIO points to a 32 byte block of memory containing Port A
registers and test registers. The remaining bytes in this
block are intended for future expansions. However, they
may be utilized as write only register locations, if desired.
TL/U/9982–21
FIGURE 19. Memory Map Partitioning
Test Logic
The HPC core contains built in test logic to aid in device
testing. This logic permits test vectors created for the stan-
dard family of products to be run while testing the Megacell
inside a cell based design. Therefore, test vector generation
to validate this complicated portion of the integrated circuit
is removed from the circuit designer. Modifications may not
be made to the test logic. Common to the strategy for all cell
based Megacells, the test logic follows the ‘‘parallel testing’’
methodology.
The parallel testing methodology isolates the core from the
remainder of the standard cell circuitry. This is accom-
plished by surrounding the core with banks of multiplexers
(see Figure 20 ). Respective multiplexer inputs and outputs
are brought to I/O pins of the device. Thus, during test the
HPC core appears as the only logic in the chip. Thirty I/O
pins are utilized by the HPC core during test. Twenty-nine of
these pins may be used for alternate functions when not in
the test mode. Sixteen pins are dedicated to Port A opera-
tion. The TEST pin determines which stimulus will reach the
core and I/O pins. This is the only I/O pin dedicated to the
test circuitry.
Two software registers assist the hardware during test. An
8-bit MUX control register (address 00FD) and a 16-bit feed-
back control register (address 00FE:00FF) are referred to
as MUXC and FDBK, respectively in the following text.
Three groups clearly define the test pins. Nine pins are out-
puts, 16 pins are bidirectional, and 5 pins are inputs. The 16
bidirectional pins are part of Port A. Port A is configured as
an address/data bus accessing the SROM address space
when in test mode. With the aid of 5:1 multiplexers and the
MUX Control register, the excessive number of outputs on
the HPC core have been brought out through 6 pins. The
outputs have been logically combined into four groups of six
outptus each. In conjunction with the TEST pin and the
MUXC register for group selection, each group is probed
separately. The ALE, NRD and NWR signals are brought out
through 2:1 MUXes.
TL/U/9982–22
FIGURE 20. HPC Core Test Logic
24
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