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參數(shù)資料
| 型號： | HPC |
| 文件頁數(shù)： | 20/30頁 |
| 文件大?。?/td> | 361K |
| 代理商： | HPC |
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Servicing the Interrupts
(Continued)
TL/U/9982–15
FIGURE 13. Block Diagram of Interrupt Logic
Reset
The RSET input initializes the processor and sets Port A in
the TRI-STATE condition. The internal data bus oscillates at
a C2 clock rate is an active high signal. If RSET is connect-
ed to logic outside of the device it should be brought in
through a schmitt trigger input. The processor vectors to
FFFF:FFFE and resumes operation at the address con-
tained at that memory location.
Timer Overview
The HPC core contains a powerful set of flexible timers en-
abling the HPC to perform extensive timer functions not
usually associated with microcontrollers.
The core contains four 16-bit timers. Timer T0 is a free-run-
ning timer, counting up at a fixed CKI/16 (Clock/16) rate. It
is used for Watchdog logic, high speed event capture and to
exit from the IDLE mode. Consequently, it cannot be
stopped or written to under software control. In addition, the
overflow of T0 is a core output, T0CY, and may be utilized
by any external logic. Upon timer overflow a pulse of width
CKI/2 occurs on T0CY. Timer T0 permits precise measure-
ments by means of the capture registers I2CR, I3CR and
I4CR. A control bit in the register T0CON configures timer
T1 and its associated register R1 as capture registers I3CR
and I2CR. The capture registers I2CR, I3CR and I4CR re-
spectively, record the value of timer T0 when specified
events occur on the interrupt pins I2, I3 and I4. The control
register IRCD programs the capture registers to trigger on
either a rising edge or a falling edge of its respective input.
The specified edge can also be programmed to generate an
interrupt (see Figure 14 ).
TL/U/9982–16
FIGURE 14. Timers T0–T1 Block
20
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