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參數(shù)資料
| 型號(hào)： | HPC |
| 文件頁(yè)數(shù)： | 22/30頁(yè) |
| 文件大?。?/td> | 361K |
| 代理商： | HPC |
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MICROWIRE/PLUS
(Continued)
TL/U/9982–19
FIGURE 17. MICROWIRE/PLUS
MICROWIRE/PLUS Operation
The HPC core can enter the MICROWIRE/PLUS mode as a
master or slave. A control bit in the IRCD register deter-
mines whether the HPC core is the master or slave mode.
An externally generated shift clock placed on the OSKI pin
is used when the HPC is configured as a slave. The OSKO
output is placed into TRI-STATE during this operation. The
shift clock is generated internally when the HPC is config-
ured as a master. The DIVBY register programs the frequen-
cy of the OSKO clock. This register allows the OSKO clock
frequency to be programmed in 14 selectable steps from
122 Hz to 1 MHz with CKI at 16.0 MHz, or from a timer T3
underflow. Hardware mode detection is provided on the MI-
CROWIRE master/slave output MWMS.
The contents of the SIO register may be accessed through
any of the memory access instructions. Data waiting to be
transmitted in the SIO register is clocked out on the falling
edge of the shift clock. Serial data on the MWIN pin is
clocked in on the rising edge of the shift clock.
Shared Memory Support
Shared memory access provides a rapid technique to ex-
change data. It is effective when data is moved from a pe-
ripheral to memory or when data is moved between blocks
of memory. A related area where shared memory access
proves effective is multiprocessing applications where two
CPUs share a common memory block. The HPC core sup-
ports shared memory access through Port A with two pins.
These pins are the NHLD input pin and the NHDA output
pin.
The host uses DMA to interface with the HPC core. A low
level on the NHLD input of the HPC core from the host
initiates a data transfer. In response, the HPC core places
Port A in a TRI-STATE mode, freeing it for use by the host.
The host waits for the acknowledge signal (NHDA) from the
HPC core indicating that the port is free. On receiving the
acknowledge, the host can rapidly transfer data into, or out
of, the shared memory by using a conventional DMA con-
troller. Upon completion of the message transfer, the host
removes the NHLD request and the HPC core resumes nor-
mal operations.
Figure 18 illustrates an application of the shared memory
interface between the HPC core and a series 32000 system.
Memory
The HPC core has been designed to offer flexibility in mem-
ory usage. A total address space of 64 kbytes can be ad-
dressed. The core contains 256 bytes of RAM, usable for
instruction execution. This 256 byte RAM block is available
as a stand alone macro for inclusion of additional memory.
Program memory addressing is controlled by the 16-bit pro-
gram counter on a byte basis. Memory can be addressed
directly by instruction or indirectly through the B, X and SP
registers. Memory can be addressed as words or bytes.
Words are always addressed on even-byte boundries. The
HPC core uses memory-mapped organization to support
registers, I/O, and on-chip peripheral functions.
The HPC core memory address space extends to 64 kbytes.
Registers and I/O are mapped as shown in Table III.
TL/U/9982–20
FIGURE 18. Shared Memory Application: HPC Core Interface to Series 32000 System
22
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