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參數(shù)資料
| 型號(hào)： | HPC |
| 文件頁數(shù)： | 19/30頁 |
| 文件大?。?/td> | 361K |
| 代理商： | HPC |
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Idle Mode
The HPC core is placed in the IDLE mode through the PSW
register. In this mode, all processor activity, except the on-
board oscillator, WATCHDOG monitoring and Timer T0, is
stopped. The HALT output bit goes high to indicate the
processor is entering the IDLE mode. As with the HALT
mode, the processor is returned to full operation by the
RSET or NMI inputs, but without waiting for oscillator stabili-
zation. A timer T0 overflow will also cause the HPC core to
resume normal operation.
Interrupts
Complex interrupt handling is easily accommodated by the
HPC core’s vectored interrupt scheme. There are eight pos-
sible interrupt sources as shown in Table II.
TABLE II. Interrupts
Vector
Address
Interrupt
Source
Arbitration
Ranking
FFFF:FFFE
RESET
0
FFFD:FFFC
Nonmaskable External on
Rising Edge of I1 Pin
1
FFFB:FFFA
External on I2 Pin
2
FFF9:FFF8
External on I3 Pin
3
FFF7:FFF6
External on I4 Pin
4
FFF5:FFF4
Timeout of Internal Timers
ORed W/External On
INT5 Pin
5
FFF3:FFF2
External on INT6 Pin
6
FFF1:FFF0
External on INT7 Pin
7
Interrupt Arbitration
The HPC core contains arbitration logic to determine which
interrupt will be serviced first if two or more interrupts occur
simultaneously. The arbitration ranking is shown in Table II.
The interrupt on reset has the highest rank and is serviced
first.
Interrupt Processing
Interrupts are serviced after the current instruction is com-
pleted except for the RSET, which is serviced immediately.
RSET, INT6 and INT7 are active high level sensitive inter-
rupts. INT5 is an external active high level sensitive interrupt
ORed with internal interrupts from timers T0 through T3.
The timer interrupts have individual enable bits. INT5 is en-
abled whenever interrupt bit 5 is high in the ENIR register.
All other interrupts are edge sensitive. NMI is positive edge
sensitive. The external interrupts on I2, I3 and I4 can be
software selected to be sensitive on a rising or falling edge.
Interrupt Control Registers
The HPC core allows the various interrupt sources and con-
ditions to be programmed. This is done through the various
control registers. A brief description of the different control
registers is given below.
Interrupt Enable Register (ENIR)
RSET and the external interrupt on I1 (NMI) are nonmaska-
ble interrupts. The other interrupts can be individually en-
abled and disabled. Additionally, a Global Interrupt Enable
Bit in the ENIR Register allows the maskable interrupts to
be collectively enabled or disabled. Thus, in order for a par-
ticular interrupt to be serviced, both the individual enable bit
and the Global Interrupt bit (GIE) have to be set.
Interrupt Pending Register (IRPD)
The IRPD register contains a bit allocated for each interrupt
vector. The occurrence of specified interrupt trigger condi-
tions causes the appropriate bit to be set. There is no indi-
cation of the order in which the interrupts have been re-
ceived. The bits are set independently of the fact that the
interrupt may be disabled. IRPD is a Read/Write register.
The bits corresponding to the maskable, external interrupts
I2–I4 are normally cleared by the HPC core after acknowl-
edging the interrupts.
For the interrupts generated internally and on bits INT5,
INT6 and INT7, the user has the responsibility of resetting
the interrupt pending flags through software.
The NMI bit is read only and I2, I3 and I4 are designed to
only allow a zero to be written to the pending bit (writing a
one has no affect). A LOAD IMMEDIATE instruction is to be
the only instruction used to clear a bit or bits in the IRPD
register. This allows a mask to be used, thus ensuring that
the other pending bits are not affected.
Interrupt Condition Register (IRCD)
Three bits of the IRCD register select the input polarity of
the external interrupts on I2, I3 and I4.
Servicing the Interrupts
The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack thus incrementing the stack
pointer (SP) twice. The Global Interrupt Enable bit (GIE) is
copied into the CGIE bit of the PSW register, it is then reset,
thus disabling further interrupts. The program counter is
loaded with the contents of the memory at the vector ad-
dress and the processor resumes operation at this point. At
the end of the interrupt service routine, the user does a
RETI instruction to pop the stack and re-enables interrupts,
or RET to just pop the stack, and then returns to the main
program. The GIE bit can be set in the interrupt service
routine to nest interrupts if desired. Figure 13 shows the
Interrupt Enable Logic.
19
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