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參數(shù)資料
| 型號(hào)： | HPC |
| 文件頁數(shù)： | 17/30頁 |
| 文件大小： | 361K |
| 代理商： | HPC |
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Standard Features
The HPC core is the building block for a number of standard
microcontrollers. Since the core is now a building block in a
cell based library, microcontroller designs are not restricted
to accessing the core solely through I/O ports. As a result,
there are several features of the core that are accessable in
the ASIC HPC core that are not accessable on the standard
microcontrollers built from the core. These features include:
Functional Descriptions
D Direct core access vs. I/O port access.
D Direct access to internal 16-bit address/data bus.
D Ability to control clock oscillations with surrounding hard-
ware.
D Ability to force a watchout condition through surrounding
hardware.
D Access to MICROWIRE/PLUS shift clock as individual
I/O pins.
D Access to Timer 2 and Timer 3 clocks as individual I/O
pins.
D General purpose 4-bit programmable clock output (used
by UART in most standard family members).
D Access to Timer 0 overflow output pulse.
D Interrupt bit 5 as a general purpose external interrupt
ORed with internal Timer interrupt.
D Access to separate RDY and HOLD input pins.
D Hardware acknowledgement of halt/idle modes (HALT
output bit).
D Ability to select which memory space addresses are af-
fected by wait states.
D Direct memory control output bits (NRD, NWR, ALE,
HBE).
D Access to hardware control bits to configure, read and
acknowledge Port A operations.
D Access to memory map block decode bits.
D Additional registers for test; Feedback control and MUX
control.
While the ASIC HPC core offers access to a greater number
of design features, it must be kept in mind that the core
does not include the peripherals found on the standard
parts. Such peripherals would include additional PWM
times, UART, A/D, HDLC and DMA channels. Some of
these peripherals are available as separate building blocks
in the cell based library.
Port A
Port A is a highly flexible 16-bit port used to communicate to
peripherals external to the integrated circuit environment.
The port may be configured as a 16-bit general purpose I/O
port or as an extension of the 16-bit address/data bus. Se-
lection is made through the EXAC pin. Port A cannot be
connected to internal logic. It must connect directly to an I/
O macro. During test, Port A is configured in the address/
data bus mode.
Port A (see Figure 12 ), consists of a data register and a
direction register. Both control registers are read/write.
The associated direction register allows the port pins to be
individually programmed as inputs or outputs. Port pins se-
lected as inputs are placed in a TRI-STATE
é
mode by re-
setting corresponding bits in the direction register. When in
the address/data bus extension mode, the direction register
is cleared.
A write operation to a port pin configured as an input causes
the value to be written into the data register. A read opera-
tion returns the value at the pin. Writing to port pins config-
ured as outputs causes the pins to assume the value written
into the Port A data register, while reading the pins returns
the value of the data register.
Address locations communicating through Port A in the ad-
dress/data bus mode should be decoded onto the RDEX
input to generate a Port A read signal.
Port A may also be configured as an 8-bit bus to support
8-bit applications. In this mode, the upper byte of the 16-bit
bus transfers addresses only. The lower byte of the bus is
used for both address and data communication. If this mode
is selected, address locations communicating through Port
A in the 8-bit mode should be decoded onto the SEL8 input.
TL/U/9982–14
*
Bidirectional I/O Macro must be selected and connected to Port A I/O pins.
FIGURE 12. Port A: I/O Structure
17
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