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參數(shù)資料
| 型號： | HI7188 |
| 廠商： | Intersil Corporation |
| 英文描述： | 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System |
| 中文描述： | 8通道，16位，精度高，Σ-ΔA / D轉(zhuǎn)換子系統(tǒng) |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 156K |
| 代理商： | HI7188 |
7-1855
Definitions
Integral Non-Linearity (INL) -
This is the maximum devia-
tion of any digital code from a straight line passing through the
endpoints of the transfer function. The endpoints of the trans-
fer function are zero scale (a point 0.5 LSB below the first
code transition 000...000 and 000...001) and full scale (a point
0.5 LSB above the last code transition 111...110 to 111...111).
Differential Non-Linearity (DNL) -
This is the deviation
from the actual difference between midpoints and the ideal
difference between midpoints (1 LSB) for adjacent codes. If
this difference is equal to or more negative than 1 LSB, a
code will be missed.
Offset Error (V
OS
) -
The offset error is the deviation of the first
code transition from the ideal input voltage (V
IN
- 0.5 LSB).
Full Scale Error (FSE) -
The full scale error is the deviation
of the last code transition from the ideal input full-scale volt-
age (V
IN
- + V
REF
/Gain - 1.5 LSB).
Input Span -
The input span defines the minimum and max-
imum input voltages the device can handle while still cali-
brating properly for gain.
End of Scan (EOS) -
The end of scan is a signal used to
indicate all active logical channels have been converted and
data is available to be read.
Line Noise Rejection -
Line noise rejection is the ability to
attenuate (reject) signals at the frequency of power lines typ-
ically 50Hz or 60Hz.
Physical/Logical Channel -
A physical channel pertains to
channels which are directly connected to the device package
pins identified in the pinout. Logical channels are predefined
in the Channel Configuration Registers (CCR) with a physical
channels reference (address) being made by the user. Refer
to the Channel Configuration Registers section for examples.
FIGURE 5. DATA READ FROM HI7188
FIGURE 6. DATA READ FROM HI7188
Waveforms
(Continued)
CS
SCLK
SDIO
SDO
t
ACC
t
DV
1ST BIT
2ND BIT
SCLK
CS
EOS
SDIO
t
EOS
8
7
6
5
1
HI7188
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI7188IN | 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System |
| HI7188IP | 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System |
| HI7191IB | 24-Bit, High Precision, Sigma Delta A/D Converter |
| HI7191 | 24-Bit, High Precision, Sigma Delta A/D Converter |
| HI7191IP | 24-Bit, High Precision, Sigma Delta A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI7188 WAF | 制造商:Harris Corporation 功能描述: |
| HI7188_00 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Channel, 16-Bit, High Precision, Sigma- Delta A/D Sub-System |
| HI7188EVAL | 功能描述:EVALUATION PLATFORM HI7188 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| HI7188IN | 功能描述:CONV A/D 16BIT 8:1 MUX 44-MQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| HI7188IP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 16BIT ADC 7188 DIP40 制造商:Harris Corporation 功能描述: |
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