參數(shù)資料
型號： HI7188
廠商： Intersil Corporation
英文描述： 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System
中文描述： 8通道，16位，精度高，Σ-ΔA / D轉(zhuǎn)換子系統(tǒng)
文件頁數(shù)： 18/22頁
文件大?。?/td> 156K
代理商： HI7188
7-1864
NOTE: When the user accesses the calibration RAMs, via the Serial
Interface, the conversion process stops, resetting the modulator, in-
tegrating filter and clearing the EOS interrupt. When the calibration
RAM I/O operation is completed the device automatically restarts be-
ginning on logical channel 1. The contents of the CR and CCR are
not affected by this I/O.
Detailed Register Descriptions
Instruction Register
The instruction register is an 8 bit register which is used dur-
ing a communications cycle for setting up read/write opera-
tions. Below are the bit assignments.
R/W -
Bit 7 of the Instruction Byte determines whether phase
2 of the communication cycle will be a read or write opera-
tion. If R/W is logic 1, a write transfer will occur in phase 2 of
the communication cycle. If R/W is logic 0, a read transfer
will occur in phase 2 of the communication cycle.
NB1, NB0 -
Bits 6 and 5 of the Instruction Byte determine the
number of bytes that will be transferred during phase 2 of a
communication cycle, if a register is selected for I/O access. If a
RAM is selected for IO access, these bits are don’t care. Any
number of bytes from 1 to 4 is allowed. See Tables 6 and 7.
RB -
Bit 4 is used to determine the byte order when accessing
a RAM address. When accessing a RAM address, if RB = 1,
the data format is most significant byte first to least significant
byte. When accessing a RAM address, if RB = 0, the data for-
mat is least significant byte first to most significant byte. When
accessing a register address, this bit is a don’t care.
A3, A2, A1, A0 -
Bits 3 and 2 (A3 and A2) of the Instruction
Byte determine which of the three internal registers will be
accessed or if both bits are set (11b), that a RAM access is
active. For register addresses, bits 1 and 0 (A1 and A0)
determine which byte of that register will be accessed first.
For RAM access (A3 = 1, A2 = 1), bits 1 and 0 (A1 and A0)
determine which RAM is the source or destination.
INSTRUCTION REGISTER (BYTE)
MSB
6
5
4
3
2
1
LSB
R/W
NB1
NB0
RB
A3
A2
A1
A0
TABLE 6. MULTIPLE BYTE ACCESS BITS
NB1, NB0 IR [6:5]
DESCRIPTION
00
Transfer 1 Byte
01
Transfer 2 Bytes
10
Transfer 3 Bytes
11
Transfer 4 Bytes
TABLE 7. INTERNAL REGISTER ADDRESS
R/W
IR [7]
NB1,
NB0
IR [6:5]
A3, A2,
A1, A0
IR [3:0]
DESCRIPTION
0/1
00
0000
CR, start byte 0, 1 byte transfer
0/1
01
0000
CR, start byte 0, 2 byte transfer
0/1
00
0001
CR, start byte 1, 1 byte transfer
0/1
01
0001
CR, start byte 1, 2 byte transfer
0/1
00
0100
CCR #1, start byte 0, 1 byte transfer
0/1
00
0101
CCR #1, start byte 1, 1 byte transfer
0/1
00
0110
CCR #1, start byte 2, 1 byte transfer
0/1
00
0111
CCR #1, start byte 3, 1 byte transfer
0/1
01
0100
CCR #1, start byte 0, 2 byte transfer
0/1
01
0101
CCR #1, start byte 1, 2 byte transfer
0/1
01
0110
CCR #1, start byte 2, 2 byte transfer
0/1
01
0111
CCR #1, start byte 3, 2 byte transfer
0/1
10
0100
CCR #1, start byte 0, 3 byte transfer
0/1
10
0101
CCR #1, start byte 1, 3 byte transfer
0/1
10
0110
CCR #1, start byte 2, 3 byte transfer
0/1
10
0111
CCR #1, start byte 3, 3 byte transfer
0/1
11
0100
CCR #1, start byte 0, 4 byte transfer
0/1
11
0101
CCR #1, start byte 1, 4 byte transfer
0/1
11
0110
CCR #1, start byte 2, 4 byte transfer
0/1
11
0111
CCR #1, start byte 3, 4 byte transfer
0/1
00
1000
CCR #2, start byte 0, 1 byte transfer
0/1
00
1001
CCR #2, start byte 1, 1 byte transfer
0/1
00
1010
CCR #2, start byte 2, 1 byte transfer
0/1
00
1011
CCR #2, start byte 3, 1 byte transfer
0/1
01
1000
CCR #2, start byte 0, 2 byte transfer
0/1
01
1001
CCR #2, start byte 1, 2 byte transfer
0/1
01
1010
CCR #2, start byte 2, 2 byte transfer
0/1
01
1011
CCR #2, start byte 3, 2 byte transfer
0/1
10
1000
CCR #2, start byte 0, 3 byte transfer
0/1
10
1001
CCR #2, start byte 1, 3 byte transfer
0/1
10
1010
CCR #2, start byte 2, 3 byte transfer
0/1
10
1011
CCR #2, start byte 3, 3 byte transfer
0/1
11
1000
CCR #2, start byte 0, 4 byte transfer
0/1
11
1001
CCR #2, start byte 1, 4 byte transfer
0/1
11
1010
CCR #2, start byte 2, 4 byte transfer
0/1
11
1011
CCR #2, start byte 3, 4 byte transfer
0
xx
1100
Data RAM burst transfer, least signifi-
cant byte first, READ ONLY
0
xx
1100
Data RAM burst transfer, most signifi-
cant byte first, READ ONLY
0/1
xx
1101
Offset RAM burst transfer, least signif-
icant byte first.
0/1
xx
1101
Offset RAM burst transfer, most sig-
nificant byte first.
0/1
xx
1110
Positive full scale RAM burst transfer,
least significant byte first.
0/1
xx
1110
Positive full scale RAM burst transfer,
most significant byte first.
0/1
xx
1111
Negative full scale RAM burst trans-
fer, least significant byte first.
0/1
xx
1111
Negative full scale RAM burst trans-
fer, most significant byte first.
TABLE 7. INTERNAL REGISTER ADDRESS (Continued)
R/W
IR [7]
NB1,
NB0
IR [6:5]
A3, A2,
A1, A0
IR [3:0]
DESCRIPTION
HI7188
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