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參數(shù)資料
| 型號： | HI7188 |
| 廠商： | Intersil Corporation |
| 英文描述： | 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System |
| 中文描述： | 8通道，16位，精度高，Σ-ΔA / D轉(zhuǎn)換子系統(tǒng) |
| 文件頁數(shù)： | 17/22頁 |
| 文件大?。?/td> | 156K |
| 代理商： | HI7188 |
7-1863
refill the four line noise rejection filters before an EOS inter-
rupt. If LNR is not enabled, it takes one conversion scan of
only the active channels before an EOS interrupt. Recalibra-
tion is not required since the calibration RAMs are not
effected by the sleep operation.
Serial Interface
The HI7188 has a flexible, synchronous serial communica-
tion port to allow easy interfacing to most industry standard
microcontrollers and microprocessors. The serial I/O is com-
patible with most synchronous transfer formats, including
both the Motorola 6805/11, SPI and Intel 8051 SSR proto-
cols. The interface supports 2-wire transfers of reading and
writing on a single bidirectional line (SDIO) or 3-wire trans-
fers of writing on SDIO and reading on the SDO line.
The Interface allows read/write access to the Control Regis-
ter, Channel Configuration Registers, and Calibration RAMs.
The interface allows read only access to the data RAM (refer
to Table 7). The interface is byte organized with each register
byte having a specific address. Single or multiple byte trans-
fers are supported. In addition, the interface allows flexibility
as to the byte and bit access order. That is, the user can
specify MSB/LSB first bit positioning and can access bytes
in ascending/descending order from any byte position.
Serial Interface Clock
The HI7188 supports two serial interface clock(SCLK)
modes for all interface timing. This allows the greatest flexi-
bility for different types of systems where the HI7188 can act
either as master in the system (it provides the serial interface
clock) or as slave (an external clock is provided to the
HI7188). These two modes are defined as self clocking and
external clocking respectively. Regardless of the clocking
mode selected, all data is registered into the HI7188 on the
rising edge of the SCLK while all data is driven out on the fall-
ing edge of SCLK. The HI7188 interface is designed to work
with clock stalling in either high or low state. The clock mode
is determined by the logic level applied to the MODE pin.
Synchronous Self Clocking
The device in a self-clocking scheme if the MODE pin is
high. This defines the SCLK pin as an output which provides
the serial clock signal used for the transfer of all data to and
from the HI7188. This self-clocking mode can be used with
processors which allow an external device to clock their
serial port. The frequency of SCLK is one eighth of the exter-
nal crystal connected between the OSC
1
and OSC
2
pins.
The HI7188 is designed for a 3.6864MHz crystal which sets
SCLK to 460.8kHz.
Synchronous External Clocking
The HI7188 is in a external clocking scheme if the MODE pin is
low. This defines the SCLK pin as an input and an external
clock must be provided to the SCLK pin. This external clocking
mode is designed for direct interface to systems which provide
a serial clock output which is synchronized to the serial data
output. The maximum frequency of the external SCLK is 5MHz.
Burst RAM Access
The Data RAM, System Offset calibration RAM, System Posi-
tive Full Scale Calibration RAM and System Negative Full
Scale Calibration RAM can
only
be accessed in a continuous
RAM “Burst”. RAM burst transfers are special instructions that
perform a continuous data transfer for all bits of that RAM.
That is, individual bytes of any RAM cannot be accessed with-
out reading all of the bytes. See Table 7. Each transfer occurs
such that the first word transferred corresponds to the first log-
ical channel converted as specified in the Channel Configura-
tion Register (CCR). The first byte transferred for each word is
controlled by the RB bit of the instruction byte and the bit posi-
tion is determined by the Control Register (CR) MSB/LSB bit.
The number of words transferred is specified by the CR bits
that describe the number of logical channels being converted
as well as the size of the destination RAM. This transfer mode
reduces the overhead of multiple IR writes as compared to
individual byte access. The following two examples are useful
in understanding the RAM burst transfer instructions.
Example 1.
The physical channel conversion order as spec-
ified by the CCRs is 8, 2, 3, 4, 5, 6, 1, 7. The HI7188 is setup
via the Control Register to convert 8 logical channels. The IR
byte written is 0xx11100 (read the data RAM). The following
occurs: After completing the IR write, 16 bytes of data will be
transferred from the HI7188. The first byte transferred will be
the most significant byte of the physical channel 8 conver-
sion results. The second byte will be the least significant
byte of the physical channel 8 conversion results. This pat-
tern of most significant byte followed by least significant byte
will repeat, in order for physical channels 2, 3, 4, 5, 6, 1, 7.
Example 2.
The physical channel conversion order as spec-
ified by the CCRs is 8, 2, 3, 4, 5, 6, 1, 7. The HI7188 is setup
via the Control Register to convert only 3 logical channels.
The IR byte written is 1xx01101 (write the offset RAM). The
following occurs: After completing the IR write, 9 bytes of
data will be written to the offset RAM (recall that the Offset
Calibration register is 3 bytes wide). The first byte is the least
significant byte used for offset calibration of physical channel
8. The second byte will be the middle byte used for offset
calibration of physical channel 8. The third byte will be the
most significant byte used for offset calibration of physical
channel 8. This pattern of least significant byte to most sig-
nificant byte will repeat for all logical channels converted in
the logical channel order as described above. For example,
the last byte transferred will be the most significant byte of
physical channel 3 used for offset calibration.
FIGURE 13A. Crystal Operation
FIGURE 13B. External CMOS clock operation
HI7188
OSC
1
OSC
2
X-3.6864MHz
6
5
HI7188
OSC
1
OSC
2
X-3.6864MHz
6
5
NOT
CONNECTED
HI7188
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI7188IN | 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System |
| HI7188IP | 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System |
| HI7191IB | 24-Bit, High Precision, Sigma Delta A/D Converter |
| HI7191 | 24-Bit, High Precision, Sigma Delta A/D Converter |
| HI7191IP | 24-Bit, High Precision, Sigma Delta A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI7188 WAF | 制造商:Harris Corporation 功能描述: |
| HI7188_00 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Channel, 16-Bit, High Precision, Sigma- Delta A/D Sub-System |
| HI7188EVAL | 功能描述:EVALUATION PLATFORM HI7188 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| HI7188IN | 功能描述:CONV A/D 16BIT 8:1 MUX 44-MQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| HI7188IP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 16BIT ADC 7188 DIP40 制造商:Harris Corporation 功能描述: |
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