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參數(shù)資料
| 型號： | HI7188 |
| 廠商： | Intersil Corporation |
| 英文描述： | 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System |
| 中文描述： | 8通道，16位，精度高，Σ-ΔA / D轉(zhuǎn)換子系統(tǒng) |
| 文件頁數(shù)： | 21/22頁 |
| 文件大?。?/td> | 156K |
| 代理商： | HI7188 |
7-1867
CS -
Chip Select. This signal is an active low input that
allows more than one device on the same serial communica-
tion lines. The SDO and SDIO will go to a high impedance
state when this signal is high. If driven high during any com-
munication cycle, that cycle will be suspended until CS reac-
tivation. Chip select can be tied low in systems that maintain
control of SCLK.
EOS -
End Of Scan. Signals the end of a logical channel
scan (all programmed logical channels have been con-
verted) and data is available for reading. EOS is useful as an
edge or level sensitive interrupt signal to a microprocessor or
microcontroller. EOS low indicates that new data is available
and the Data RAM can be read. EOS will return high upon
completion of a complete Data RAM read cycle. Please refer
to the Data RAM section for details.
CA -
Calibration Active. This pin is high if any active logical
channel is in the calibration mode and stays high for the
entire scan period. CA checks only those channels that are
actively being converted on. For example, if the HI7188 is
programmed to convert only two channels and any of the
CCR bytes of the six nonactive channels are in the calibra-
tion mode, CA will NOT go active. The user can monitor the
CA output to determine when all active channels have com-
pleted calibration.
MODE -
Mode. This input is used to select between Syn-
chronous Self Clocking Mode (high) or the Synchronous
External Clocking Mode (low).
RSTI/O -
Reset I/O. This active low asynchronous input is
used to reset the serial interface state machine. This reset
only affects the I/O logic and does not affect the Control Reg-
ister, Channel Configuration Register or Calibration RAMs.
This effectively aborts any communication cycle and places
the device in a standby mode awaiting the next IR cycle.
Serial Interface Communication
It is useful to think of the HI7188 interface in terms of communi-
cation cycles. Each communication cycle happens in 2 phases.
The first phase is the writing of an instruction byte while the
second phase is the data transfer as described by the instruc-
tion byte. It is important to note that phase 2 of the communica-
tion cycle can be a single byte or a multi-byte transfer of data
including a Burst RAM read/write. It is up to the user to maintain
synchronism with respect to data transfers. If the system pro-
cessor “gets lost”, during an I/O operation, the only way to
recover is to reset the Serial Interface via a RSTI/O. Figure 15
shows both a 2-wire and a 3-wire data transfer.
Instruction Byte Phase
The instruction byte phase initiates a data transfer
sequence. The processor writes an eight bit byte to the
“Instruction Register”, known as the “Instruction Byte”. The
instruction byte informs the HI7188 about the Data cycle
phase activities and includes the following information:
Read or Write Cycle
Number of Bytes to be Transferred
Which Register and Starting Byte to be Accessed
Data Cycle Phase
In the data cycle phase, data transfer takes place as defined
by the Instruction Register Byte. See Write Operation and
Read Operation sections for detailed descriptions. It is
important to note that phase 2 of the communication cycle
can be a multi-byte transfer of data.
For example, the 4 byte Channel Configuration register can be
read using one multi-byte communication cycle rather than four
single byte communication cycles. After phase 2 is completed
the HI7188 I/O logic enters a standby mode while waiting to
receive a new instruction byte. It is up to the user to maintain
synchronism with respect to data transfers. If the system pro-
cessor “gets lost” the only way to recover is to reset the HI7188.
Serial Interface Format
Several formats are available for reading from and writing to
the HI7188 registers in both the 2-wire and 3-wire protocols.
Please refer to Figure 15. A portion of these formats is con-
trolled by the CR<2:1> (BD and MSB) bits which control the
byte direction and bit order of a data transfer respectively.
These two bits can be written in any combination but only
the two most useful will be discussed here. The first combi-
nation is to reset both the BD and MSB bits (BD = 0,
MSB = 0). This sets up the interface for descending byte
order and MSB first format. When this combination is used
the user should always write the instruction register such
that the starting byte is the most significant byte address. For
example, read three bytes of data starting with the most sig-
nificant byte. The first byte read will be the most significant in
MSB to LSB format. The next byte will be the next least sig-
nificant (recall descending byte order) again in MSB to LSB
order. The last byte will be the next lesser significant byte in
MSB to LSB order. THE ENTIRE WORD WAS READ MSB
TO LSB format. The second combination is to set both the
BD and MSB bits to 1. This sets up the interface for ascend-
ing byte order and LSB first format. When this combination is
used the user should always write the instruction register
such that the starting byte is the least significant byte
address. For example, read three bytes of data starting with
the least significant byte. The first byte read will be the least
significant in LSB to MSB format. The next byte will be the
next greater significant (recall ascending byte order) again in
LSB to MSB order. The last byte will be the next greater sig-
nificant byte in LSB to MSB order. THE ENTIRE WORD
WAS READ LSB TO MSB format. After completion of each
communication cycle, The HI7188 interface enters a standby
mode while waiting to receive a new instruction byte.
INSTRUCTION
BYTE
DATA
BYTE 1
DATA
BYTE 2
DATA
BYTE 3
INSTRUCTION
CYCLE
DATA CYCLE
CS
SDIO
SDO
FIGURE 15. 3-WIRE, 3 BYTE READ TRANSFER
HI7188
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PDF描述 |
|---|---|
| HI7188IN | 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System |
| HI7188IP | 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System |
| HI7191IB | 24-Bit, High Precision, Sigma Delta A/D Converter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI7188 WAF | 制造商:Harris Corporation 功能描述: |
| HI7188_00 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Channel, 16-Bit, High Precision, Sigma- Delta A/D Sub-System |
| HI7188EVAL | 功能描述:EVALUATION PLATFORM HI7188 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| HI7188IN | 功能描述:CONV A/D 16BIT 8:1 MUX 44-MQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| HI7188IP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 16BIT ADC 7188 DIP40 制造商:Harris Corporation 功能描述: |
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