參數(shù)資料
型號(hào)： HI7188
廠商： Intersil Corporation
英文描述： 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System
中文描述： 8通道，16位，精度高，Σ-ΔA / D轉(zhuǎn)換子系統(tǒng)
文件頁(yè)數(shù)： 19/22頁(yè)
文件大小： 156K
代理商： HI7188
7-1865
Control Register
The Control Register (CR) is 16 bits wide and contains infor-
mation that determines operating mode and the system/chip
level configuration. This configuration applies to all logical
channels and cannot be modified at the channel level. Fol-
lowing are the bit assignments:
T3, T2, T1 -
Bits 15, 14 and 13 are reserved and MUST
always be logic zero for normal operation. These bits are low
after RESET is applied.
CHOP.
Bit 12 is the active low chop bit used to determine
whether the chopper stabilized amplifier is used or
bypassed. This bit is low (chop on) after RESET is applied.
SE.
Bit 11 is the active high suppress EOS bit. If high, the
EOS interrupt will not go active when any logical channel is
in calibration mode. If this bit is high and no logical channels
are in the calibration mode, or this bit is low, EOS functional-
ity is as previously described. This bit allows the user to sup-
press false EOS interrupts during calibration. Only logical
channels that are actively being converted are considered.
That is, if only two logical channels are being converted but
the CCR byte for a non active logical channel is in a calibra-
tion mode, the EOS functionality is active. This bit is low
(suppress EOS off) after RESET is applied.
LNR.
Bit 10 is the active high line noise rejection(LNR) bit. If
high LNR is selected. This bit is low (LNR off) after RESET is
applied.
FS.
Bit 9 is the 50Hz/60Hz frequency select bit. If bit 9 is
high, the clock generation logic synchronizes conversions for
proper rejection of 50Hz line noise. If bit 9 is low, the clock
generation logic synchronizes conversions for proper rejec-
tion of 60Hz line noise. This bit is low (60Hz LNR) after
RESET is applied.
TC.
Bit 8 is the active high two’s complement bit used to select
between 2’s complementary and offset binary data coding for
bipolar mode. In bipolar mode, a high selects two’s comple-
ment; when low data is offset binary. Note that in unipolar
mode the binary data coding is not affected by the TC bit. This
bit is low (offset binary data) after RESET is applied.
N2, N1, N0.
Bits 7, 6 and 5 are the bits that specify the number
of active logical channels to be converted. See Table 8. These
bits are low (one active channel) after RESET is applied.
TP -
Bit 4 is the active high two point calibration bit. When
high, the positive gain slope factor is used for both positive
and negative voltages. This bit is low (normal three point cal)
after RESET is applied.
SLP -
Bit 3 is the active high sleep mode bit used to put the
device in a low power/standby mode. When high, conversion
stops and the conversion pointer is reset to logical channel
1. The four line noise rejection filters are cleared and EOS is
deactivated. The serial interface, calibration/data RAMs, CR
and CCR are not affected.
To return from sleep mode the user changes this bit from
high to low. This restarts the conversion process beginning
with logical channel 1. If line noise rejection is enabled, it
takes four complete scans (all active channels) to refill the
four line noise rejection filters before an EOS interrupt. If line
noise rejection not enabled, it takes 1 complete scan before
an EOS interrupt.
This bit is low (sleep mode off) after RESET is applied.
BD.
Bit 2 is the byte direction bit used to determine either
ascending or descending order access for multi-byte trans-
fers. When high, ascending order is enabled. When low,
descending order is enabled. This bit is low (descending
order) after RESET is applied.
MSB.
Bit 1 bit direction bit used to select whether a serial
data transfer is MSB or LSB first. When low, MSB first mode
is enabled while high selects LSB first. This bit is low (MSB
first) after RESET is applied.
SDL.
Bit 0 selects a two-wire or three-wire transfer protocol of
the serial interface. When low, two-wire data transfers are done
using the SDIO pin. Both data in and out of the part is uses the
by-directional SDIO pin. When high, three-wire data transfers
are done using the SDIO and SDO pins. Data into the part uses
the SDIO pin while data out uses the SDO pin. This bit is low
(two-wire, SDIO exclusively) after RESET is applied.
Channel Configuration Registers
The HI7188 Channel Configuration Registers (CCR) comprise
a 64-bit memory element that defines the logical channel con-
version order as well as each logical channel specific data such
as physical channel address, mode, gain, and bipolar/unipolar
operation. The 64 bits are divided into two 32 bit register blocks
referred to as CCR#2 and CCR#1. Each register contains four
CONTROL REGISTER BYTE 1
MSB
14
13
12
11
10
9
LSB
T3
T2
T1
CHOP
SE
LNR
FS
TC
CONTROL REGISTER BYTE 0
MSB
6
5
4
3
2
1
LSB
N2
N1
N0
TP
SLP
BD
MSB
SDL
TABLE 8. NUMBER OF CONVERSION CHANNELS
N2, N1, N0 CR [7:5]
NUMBER OF CHANNELS TO CONVERT
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
8
HI7188
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