參數(shù)資料
型號: HD66787
廠商: Renesas Technology Corp.
英文描述: 528-channel, One-chip Driver with 262,144-color Display RAM and Power Supply Circuit for Low-temperature Poli-Si TFT (LTPS-TFT) Panels with Incorporat
中文描述: 528與262,144色顯示RAM和低電源電路通道,單芯片驅(qū)動器的溫度和旋鈴聲非晶硅TFT(薄膜晶體管)與Incorporat小組
文件頁數(shù): 56/159頁
文件大小: 1607K
代理商: HD66787
HD66787
Preliminary
Rev.0.22, May.23.2003, page 56 of 159
VCM4
VCM3
VCM2
VCM1
VCM0
VcomH
VDV4
VDV3
VDV2
VDV1
VDV0
Vcom amplitude
0
0
0
0
0
VREG1OUT x 0.40
0
0
0
0
0
VREG1OUT x 0.60
0
0
0
0
1
VREG1OUT x 0.42
0
0
0
0
1
VREG1OUT x 0.63
0
0
0
1
0
VREG1OUT x 0.44
0
0
0
1
0
VREG1OUT x 0.66
:
:
:
:
:
:
:
:
:
:
:
:
0
1
1
0
0
VREG1OUT x 0.64
0
1
1
0
0
VREG1OUT x 0.96
0
1
1
0
1
VREG1OUT x 0.66
0
1
1
0
1
VREG1OUT x 0.99
0
1
1
1
0
VREG1OUT x 0.68
0
1
1
1
0
VREG1OUT x 1.02
0
1
1
1
1
Halt internal volume.
Adjust with a variable
external resistor from
VcomR.
VREG1OUT x 0.70
0
1
1
1
1
Setting disabled
1
0
0
0
0
1
0
0
0
0
VREG1OUT x 1.05
1
0
0
0
1
VREG1OUT x 0.72
1
0
0
0
1
VREG1OUT x 1.08
1
0
0
1
0
VREG1OUT x 0.74
1
0
0
1
0
VREG1OUT x 1.11
:
:
:
:
:
:
1
0
0
1
1
VREG1OUT x 1.14
1
1
1
0
0
VREG1OUT x 0.94
1
0
1
0
0
VREG1OUT x 1.17
1
1
1
0
1
VREG1OUT x 0.96
1
0
1
0
1
VREG1OUT x 1.20
1
1
1
1
0
VREG1OUT x 0.98
1
0
1
1
0
VREG1OUT x 1.23
1
0
1
1
Setting disabled
1
1
1
1
1
Halt internal volume.
Adjust with a variable
external resistor from
VcomR.
1
1
*
*
*
Setting disabled
Note 1) Adjust VREG1OUT and VCM0-4 to set VcomH the same level as VDH or less.
Note 2) Adjust VREG1OUT and VDV0-4 to set the amplitude of Vcom 6.0V or less.
RAM Address Set (R21h)
AD15–0:
Make the initial setting for the GRAM address in the address counter (AC). After GRAM data
are written, the address counter is automatically updated according to the settings with AM, I/D bits and the
setting for a new GRAM address is not required in the address counter. Therefore, data are written
consecutively without resetting the address. The address counter is not automatically updated when data
are read out from GRAM.
GRAM address setting can not be made during the standby mode. An address set should be made within
the area specified with the window address.
When the RGB interface is selected (RM = 1), the setting of the address for AD15-0 is made every frame at
the falling edge of VSYNC. When the internal clock operation or VSYNC interface is selected (RM = 0),
the setting of the address is made when the instruction is executed.
R/W RS
IB15 IB14 IB13 IB12 IB11 IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3 IB2
IB1
IB0
W
1
AD
0
AD
15
AD
14
AD
13
AD
12
AD
11
AD
10
AD
9
AD
7
AD
6
AD
5
AD
4
AD
3
AD
2
AD
1
AD
8
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