參數(shù)資料
型號: HD66787
廠商: Renesas Technology Corp.
英文描述: 528-channel, One-chip Driver with 262,144-color Display RAM and Power Supply Circuit for Low-temperature Poli-Si TFT (LTPS-TFT) Panels with Incorporat
中文描述: 528與262,144色顯示RAM和低電源電路通道,單芯片驅(qū)動器的溫度和旋鈴聲非晶硅TFT(薄膜晶體管)與Incorporat小組
文件頁數(shù): 150/159頁
文件大?。?/td> 1607K
代理商: HD66787
HD66787
Preliminary
Rev.0.22, May.23.2003, page 150 of 159
RGB interface timing characteristics
18/16 bit RGB interface (HWM =1), Vcc = 1.8V to 2.4V
Item
Symbol
Unit
Test
Condition
Figure 5
min.
typ.
max.
VSYNC/HSYNC Set up time
tSYNCS
clock
0
1
ENABLE Set up time
tENS
ns
Figure 5
20
ENABLE Hold time
tENH
ns
Figure 5
80
VLD Set up time
20
VLD Hold time
tVLH
ns
Figure 5
80
DOTCLK “Low” Level pulse
width
PWDL
ns
Figure 5
90
DOTCLK “High” Level pulse
width
PWDH
ns
Figure 5
90
DOTCLK cycle time
tCYCD
ns
Figure 5
200
Data Set up time
tPDS
ns
Figure 5
20
Data Hole time
tPDH
ns
Figure 5
80
DOTCLK, VSYNC, HSYNC
rising and falling time
trgbr, trgbf
ns
Figure 5
25
18/16 bit RGB interface (HWM = 1), Vcc = 2.4V to 3.7 V
Item
Symbol
Unit
Test
Condition
Figure 5
min.
typ.
max.
VSYNC/HSYNC Set up time
tSYNCS
clock
0
1
ENABLE Set up time
tENS
ns
Figure 5
10
ENABLE Hold time
tENH
ns
Figure 5
20
VLD Set up time
10
VLD Hold time
tVLH
ns
Figure 5
40
DOTCLK “Low” Level pulse
width
PWDL
ns
Figure 5
40
DOTCLK “High” Level pulse
width
PWDH
ns
Figure 5
40
DOTCLK cycle time
tCYCD
ns
Figure 5
100
Data Set up time
tPDS
ns
Figure 5
10
Data Hole time
tPDH
ns
Figure 5
40
DOTCLK, VSYNC, HSYNC
rising and falling time
trgbr, trgbf
ns
Figure 5
25
T.B.D.
T.B.D.
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