HD66787
Preliminary
Rev.0.22, May.23.2003, page 15 of 159
PAD Arrangement
n
Chip Size : 20.50mm×2.80mm
n
Chip Thickness : 550
μ
m (typ.)
n
Pad Coordinate: PAD Center
n
Coordinate Origin : Chip center
n
Au bump size :
(1) 80
μ
m x 80
μ
m
Corner dummy
No.1, No211, No.229, No.768
(2)54
μ
m×100
μ
m
Input :
No.2 ~ No.210 ,
No.230 ~ No.234 , No.763 ~ No.767
(3)100
μ
m×54
μ
m
Input :
No.212 ~ No.228 , No.769 ~ No.791
(4)33
μ
m×77
μ
m
Laced LCD output side:
No.235 ~ No.762
n
Au bump pitch : see PAD coordinate
n
Au bump height :15
μ
m (typ.)
n
Numbers in the figure indecates numbers of
PAD coordinate
n
Alignment mark
(1) Arrangement : 2 places
Coordinate(X,Y)= (-9394.4, 1214.7)
Coordinate(X,Y)= (9394.4, 1214.7)
100
μ
m
(2-a) Coordinate(X,Y) =( -10024.0,1264.6)
(2-b) Coordinate(X,Y) =( 10024.0,1264.6)
(3-a)Coordinate (X,Y) = (-10114.6, 1160.7)
(3-b)Coordinate (X,Y) = (10114.6, 1160.7)
50
μ
m
50
μ
m
20
10
25
25
10
1
2
2
1
70
μ
m
7
μ
m
10
25
25
10
1
5
2
2
1
5
5
5
80
μ
m
70
μ
m
8
μ
m
7
μ
m
30
40
30
5
3
4
3
50
1
μ
m
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
D
S
S
S
S
DUMMY1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TESTO2
C22+
C22+
C22-
C22-
C21+
C21+
C21-
C21-
C12+
C12+
C12+
C12+
C12-
C12-
C12-
C12-
1
1
1
Vcom1
Vcom1
Vcom1
Vcom1
Vcom1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S1
S2
S3
S4
S5
1
1
1
1
1
1
1
1
1
DUMMY2
DUMMY3
DUMMY4
DUMMY5
DUMMY6
DUMMY7
DUMMY8
DUMMY9
DUMMY10
IOGNDDUM1
LSEL12
LSEL11
LSEL10
LSEL20
LSEL21
LSEL22
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IM0/ID
IM1
IM2
IM3
1
1
1
1
IOVccDUM1
RESET*
1
1
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
1
1
1
1
1
1
1
1
1
IOGNDDUM2
1
DB8
DB7
DB6
DB5
DB4
DB3
DB2
1
1
1
1
1
1
1
DB1/SDO
DB0/SDI
IOVccDUM2
1
1
1
RD*
1
WR*/SCL
1
RS
CS*
VLD
1
1
1
IOGNDDUM3
VSYNC
HSYNC
DOTCLK
ENABLE
IOVccDUM3
1
1
1
1
1
1
PD17
PD16
PD15
PD14
PD13
PD12
1
1
1
1
1
1
IOGNDDUM4
1
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
FLM
IOVcc
IOVcc
Vcc
Vcc
Vcc
Vcc
RVcc
RVcc
RVcc
RVcc
RVcc
Vci
Vci
Vci
Vci
Vci
Vci
VciLVL
RGND
RGND
RGND
RGND
RGND
RGND
AGND
AGND
AGND
AGND
AGND
GND
GND
GND
GND
GND
GND
TEST1
TEST2
OSC1
OSC2
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DUMMYR1
DUMMYR2
DUMMYR3
DUMMYR4
DUMMYR5
DUMMYR6
DUMMYR7
DUMMYR8
DUMMYR9
DUMMY11
DUMMY12
DUMMY13
DUMMY14
DUMMY15
DUMMY16
DUMMY17
DUMMY18
DUMMY19
DUMMY20
DUMMY21
DUMMY22
DUMMY23
DUMMY24
DUMMY25
DUMMY26
DUMMY27
DUMMY28
DUMMY29
DUMMY30
DUMMY31
DUMMY32
DUMMY33
DUMMY34
DUMMY35
DUMMY36
DUMMY37
DUMMY38
REGP
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VGS
VGS
V0P
V0N
1
1
1
1
VMONI
V31P
V31N
TESTA4
TESTA1
VcomR
VREG1OUT
TESTA2
VTESTS
1
1
1
1
1
1
1
1
1
VCL
VCL
1
1
VLOUT4
1
Vci1
Vci1
Vci1
1
1
1
VciOUT
VciOUT
VciOUT
DDVDH
DDVDH
DDVDH
VLOUT1
VLOUT1
C11-
C11-
C11-
C11-
C11+
C11+
C11+
C11+
1
1
1
1
S524
S525
S526
S527
S528
1
1
1
1
1
1
1
1
1
1
1
1
1
Vcom2
Vcom2
Vcom2
Vcom2
Vcom2
1
1
1
1
1
1
1
1
1
DUMMY39
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TESTO1
V
V
V
V
V
V
V
V
V
V
V
V
D
S
S
S
S
HD667B87
Laced Output
Arrangement
Top View
No.1
No.791
No.210
No.235
No.768
No.769
Y
X
M
2
M
5
Min 80um pich
23 pin
Min 80um pich
17 pin
Short-circuit
within
the chip
No.762
No.2
No.211
No.212
No.228
No.229
No.230
No.767