Flowchart for Erasing Multiple Blocks
Figure 18-18 Multiple-Block Erase Flowchart
Start
Write 0 data to all addresses to be
erased (prewrite)
*
1
n = 1
Set erase block registers
(set bits of blocks to be erased to 1)
Enable watchdog timer
Wait initial value setting x = 6.25 ms
*
2
Select erase mode (E bit = 1 in FLMCR)
Wait (x) ms
Clear E bit
Disable watchdog timer
Select erase-verify mode
(EV bit = 1 in FLMCR)
Wait (t
VS1
)
μ
s
Set top address of block as
verify address
Dummy write to verify address
(flash memory latches address)
3
*
Erase-verify
next block
Verify
*
4
(read memory)
Last
address in block
Address + 1
→
address
Clear EBR bit of erase-verified block
All erased blocks
verified
Clear EV bit
All blocks erased
(EBR1 = EBR2 = 0)
End of erase
n
≥
N
Yes
Erase error
n + 1
→
n
No
No
Yes
No
No
Yes
No
Yes
No good
OK
Erasing ends
All erased blocks
verified
Erase-verify next block
Yes
No
Yes
V E
Clear bit
Clear erase block registers
(clear bits of blocks to be erased to 0)
n
≥
4
Wait (t
VS2
)
μ
s
Wait (z)
μ
s
V E
Clear bit
Set V E bit
(V E bit = 1 in FLMCR)
Double the erase time (x
×
2
→
x)
Notes: 1. Program all addresses to be erased by
following the prewrite flowchart.
2. Set the watchdog timer overflow interval to
the value indicated in table 18-15.
3. For the erase-verify dummy write, write H'FF
with a byte transfer instruction.
4. When erasing two or more blocks, clear the
bits of erased blocks in the erase block
register, so that only unerased blocks will be
erased again.
5. t
VS1
: 4 μs
z:
5 to 10 μs
t
VS2
: 2 μs
N:
6. The erase time x is successively
incremented by the initial set value
×
2
n–1
(n = 1, 2, 3, 4). An initial
value of 10 ms or less should be
set, and the time for one erasure
should be 50 ms or less.
602
600