
Table 1-1 Features
Feature
CPU
Description
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
Sixteen 16-bit general registers
(also usable as + eight 16-bit registers or eight 32-bit registers)
High-speed operation (flash memory version)
Maximum clock rate: 16 MHz
Add/subtract: 125 ns
Multiply/divide: 875 ns
High-speed operation (masked ROM and PROM versions)
Maximum clock rate: 18 MHz
Add/subtract: 111 ns
Multiply/divide: 778 ns
16-Mbyte address space
Instruction features
8/16/32-bit data transfer, arithmetic, and logic instructions
Signed and unsigned multiply instructions (8 bits
×
8 bits, 16 bits
×
16 bits)
Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
Bit accumulator function
Bit manipulation instructions with register-indirect specification of bit positions
H8/3048
ROM: 128 kbytes
RAM: 4 kbytes
Memory
H8/3047
ROM: 96 kbytes
RAM: 4 kbytes
H8/3045
ROM: 64 kbytes
RAM: 2 kbytes
H8/3044
ROM: 32 kbytes
RAM: 2 kbytes
Interrupt
controller
Seven external interrupt pins: NMI, IRQ
0
to IRQ
5
30 internal interrupts
Three selectable interrupt priority levels
Bus controller
Address space can be partitioned into eight areas, with independent bus
specifications in each area
Chip select output available for areas 0 to 7
8-bit access or 16-bit access selectable for each area
Two-state or three-state access selectable for each area
Selection of four wait modes
Bus arbitration function
2