Table 1-1 Features (cont)
Feature
Refresh
controller
Description
DRAM refresh
Directly connectable to 16-bit-wide DRAM
CAS-before-RAS refresh
Self-refresh mode selectable
Pseudo-static RAM refresh
Self-refresh mode selectable
Usable as an interval timer
DMA controller
(DMAC)
Short address mode
Maximum four channels available
Selection of I/O mode, idle mode, or repeat mode
Can be activated by compare match/input capture A interrupts from ITU
channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI
channel 0, or external requests
Full address mode
Maximum two channels available
Selection of normal mode or block transfer mode
Can be activated by compare match/input capture A interrupts from ITU
channels 0 to 3, external requests, or auto-request
16-bit integrated Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10
timer unit (ITU)
pulse inputs
16-bit timer counter (channels 0 to 4)
Two multiplexed output compare/input capture pins (channels 0 to 4)
Operation can be synchronized (channels 0 to 4)
PWM mode available (channels 0 to 4)
Phase counting mode available (channel 2)
Buffering available (channels 3 and 4)
Reset-synchronized PWM mode available (channels 3 and 4)
Complementary PWM mode available (channels 3 and 4)
DMAC can be activated by compare match/input capture A interrupts
(channels 0 to 3)
Programmable
timing pattern
controller (TPC)
Maximum 16-bit pulse output, using ITU as time base
Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)
Non-overlap mode available
Output data can be transferred by DMAC
Watchdog
timer (WDT),
1 channel
Reset signal can be generated by overflow
Reset signal can be output externally
Usable as an interval timer
Serial
communication
interface (SCI),
2 channels
Selection of asynchronous or synchronous mode
Full duplex: can transmit and receive simultaneously
On-chip baud-rate generator
Smart card interface functions added (SCI0 only)
3