參數(shù)資料
型號: HC05K3GRS
英文描述: 68HC05K3 General Release Specification
中文描述: 68HC05K3一般版本規(guī)范
文件頁數(shù): 71/132頁
文件大?。?/td> 1188K
代理商: HC05K3GRS
MC68HC05K3 — Revision 4.0
Technical Data
MOTOROLA
8-Bit Timer
71
Technical Data — MC68HC05K3
Section 8. 8-Bit Timer
8.1 Contents
8.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
8.3
8.3.1
8.3.2
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Timer Status/Control Register . . . . . . . . . . . . . . . . . . . . . . .74
8.4
COP Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
8.5
Operating During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .77
8.6
Operating During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .77
8.2 Introduction
The timer for this device is an 8-bit ripple counter. The features include
timer overflow (TOF), power-on reset (POR), real-time interrupt (RTI),
and computer operating properly (COP) watchdog timer. This timer is
powered down in the stop mode to reduce STOP I
DD
.
As shown in
Figure 8-1
, the timer is driven by the timer clock, NTF1,
divided by four (4). NTF1 has the same phase and frequency as the
processor bus clock, PH2, but is not stopped by the wait or halt modes.
This signal drives an 8-bit ripple counter. The value of this 8-bit ripple
counter can be read by the CPU at any time by accessing the timer
counter register (TCNTR) at address $09. A timer overflow function is
implemented on the last stage of this counter, giving a possible interrupt
at the rate of f
OP
/1024. Two additional stages produce the POR function
at f
OP
/4064 or f
OP
/16, followed by two more stages, with the resulting
clock (f
OP
/16,384) driving the real-time interrupt (RTI) circuit.
The RTI circuit consists of three divider stages with a one-of-four
selector. The output of the RTI circuit is further divided by eight to drive
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