參數(shù)資料
型號: HC05K3GRS
英文描述: 68HC05K3 General Release Specification
中文描述: 68HC05K3一般版本規(guī)范
文件頁數(shù): 43/132頁
文件大?。?/td> 1188K
代理商: HC05K3GRS
Interrupts
Hardware Interrupts
MC68HC05K3 — Revision 4.0
TechnicalData
MOTOROLA
Interrupts
43
4.6 Hardware Interrupts
All hardware interrupts except RESET are maskable by the I bit in the
CCR. If the I bit is set, all hardware interrupts (internal and external) are
disabled. Clearing the I bit enables the hardware interrupts. The two
types of hardware interrupts are explained here.
4.6.1 External Interrupt (IRQ)
The IRQ pin provides an asynchronous interrupt to the CPU. A block
diagram of the IRQ function is shown in
Figure 4-3
.
The IRQ pin is one source of an IRQ interrupt, and a mask option is
available to enable the four lower order port A pins (PA0–PA3) to act as
other IRQ interrupt sources. All of these sources are combined into a
single ORing function that is latched by the IRQ latch.
The IRQ latch is set on the falling edge of the IRQ pin or on the rising
edge of a PA0–PA3 pin, if port A interrupts have been enabled by the
mask option.
Figure 4-3. IRQ Function Block Diagram
LATCH
R
V
DD
IRQ PIN
I
RQE
IRQ SENSITIVITY
MASK OPTION
IRQF
TO IRQ
PROCESSING
IN CPU
IRQ VECTOR FETCH
TO BIH & BIL
INSTRUCTION
SENSING
RST
PORT A IRQ
MASK OPTION
PA0
PA1
PA2
PA3
IRQR
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