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| 型號(hào)： | HC05K3GRS |
| 英文描述： | 68HC05K3 General Release Specification |
| 中文描述： | 68HC05K3一般版本規(guī)范 |
| 文件頁(yè)數(shù)： | 24/132頁(yè) |
| 文件大小： | 1188K |
| 代理商： | HC05K3GRS |
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Technical Data
MC68HC05K3 — Revision 4.0
24
General Description
MOTOROLA
General Description
1.7.2.5 External C lock
An external clock from another CMOS-compatible device can be
connected to the OSC1 input, with the OSC2 input not connected, as
shown in
Figure 1-5
(d)
. This configuration is possible regardless of
whether the oscillator is set up for crystal/ceramic resonator, 2-pin RC,
or 3-pin RC operation. However, if the 3-pin RC oscillator is selected, the
PB1/OSC3 pin also must be left unconnected.
1.7.3 Reset (RESET)
This pin can be used as an input to reset the MCU to a known startup
state by pulling the pin to the low state. The RESET pin contains a
steering diode to discharge any voltage on the pin to V
DD
when the
power is removed. The RESET pin contains an internal pullup resistor to
V
DD
of approximately 100 k
to allow the RESET pin to be left
unconnected for low-power applications. The RESET pin contains an
internal Schmitt trigger to improve its noise immunity as an input.
The RESET pin has an internal pulldown device that pulls the RESET
pin low when there is an internal COP watchdog or an illegal address
reset. Refer to
Section 5. Resets
.
1.7.4 Maskable Interrupt Request (IRQ)
The IRQ input pin drives the asynchronous IRQ interrupt function of the
CPU. The IRQ interrupt function has a mask option to select either
negative edge-sensitive triggering or both negative edge-sensitive and
low level-sensitive triggering. If the option is selected to include
level-sensitive triggering, the IRQ pin requires an external resistor to
V
DD
if “wired-OR” operation is desired. If the IRQ pin is not used, it must
be tied to the V
DD
supply.
NOTE:
Each of the PA0–PA3 I/O pins can be connected through an OR gate to
the IRQ interrupt function by a common mask option. This capability
allows keyboard scan applications where the transitions or levels on the
I/O pins behave the same as the IRQ pin, except that the logic level is
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