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參數(shù)資料
| 型號： | HC05K3GRS |
| 英文描述： | 68HC05K3 General Release Specification |
| 中文描述： | 68HC05K3一般版本規(guī)范 |
| 文件頁數(shù)： | 46/132頁 |
| 文件大小： | 1188K |
| 代理商： | HC05K3GRS |
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Technical Data
MC68HC05K3 — Revision 4.0
46
Interrupts
MOTOROLA
Interrupts
IRQF — IRQ Interrupt Request Bit
The IRQF flag bit indicates that an IRQ request is pending. Writing to
the IRQF flag bit has no effect on it. The IRQF flag bit is cleared
automatically when the IRQ vector is fetched and the service routine
is entered. The IRQF flag bit also can be cleared by writing a logic 1
to the IRQR acknowledge bit to clear the IRQ latch and also condition
theexternalIRQsourcestobeinactiveiftheedge-andlevel-sensitive
maskoptionisselected.Inthisway,anyadditionalsettingoftheIRQF
flag bit while in the service routine can be ignored by clearing the
IRQF flag bit just before exiting the service routine. If the IRQF flag bit
is set again while in the IRQ service routine, the CPU re-enters the
IRQ interrupt sequence unless the IRQF flag bit is cleared. The IRQF
flag bit is cleared by reset.
IRQE — IRQ Interrupt Enable Bit
The IRQE bit enables or disables the IRQF flag bit to initiate an IRQ
interrupt sequence. If the IRQE enable bit is set, the IRQF flag bit can
generate an interrupt sequence. If the IRQE enable bit is cleared, the
IRQF flag bit cannot generate an interrupt sequence. Reset sets the
IRQE enable bit, thereby enabling IRQ interrupts once the I bit is
cleared. Execution of the STOP or WAIT instructions causes the
IRQE bit to be set to allow the external IRQ to exit these modes. In
addition, reset also sets the I bit, which masks all interrupt sources.
NOTE:
If the I bit is cleared, any instruction that sets the IRQE enable bit when
the IRQF flag bit is already set initiates an IRQ interrupt sequence
immediately after that instruction.
4.6.3 Port A Interrupts (PA0–PA3)
The IRQ interrupt also can be triggered by inputs to PA0–PA3 port pins
as described in
4.6.1 External Interrupt (IRQ)
if the port interrupts mask
option is used. If enabled, the lower four bits of port A can activate the
IRQ interrupt function and the interrupt operation is the same as the
input to the IRQ pin. The mask option allows all of these input pins to be
ORed with the input present on the IRQ pin. All PA0–PA3 pins must be
selected as a group and as an additional IRQ interrupt source. All the
port A interrupt sources also are controlled by the IRQE enable bit.
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