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參數(shù)資料
| 型號： | HC05K3GRS |
| 英文描述： | 68HC05K3 General Release Specification |
| 中文描述： | 68HC05K3一般版本規(guī)范 |
| 文件頁數(shù)： | 62/132頁 |
| 文件大?。?/td> | 1188K |
| 代理商： | HC05K3GRS |
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Technical Data
MC68HC05K3 — Revision 4.0
62
Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
The PDRA is a write-only register and any reads of location $0010 return
undefined results. Since reset clears both the DDRA and the PDRA, all
pins initialize as inputs with the pulldown devices active (if enabled by
mask option).
7.3.4 Port A Light-Emitting Diode (LED) Drive Capability
The outputs of port A pins 4–7 are capable of sinking high current for
light-emitting diode (LED) drive capability.
7.3.5 Port A I/O Pin Interrupts
The inputs for the lower four bits of port A can be connected through an
OR gate to the IRQ latched input to the CPU by a mask option. When
connected as an alternate source of an IRQ interrupt, the port A input
pins behave the same as the IRQ pin itself, except that their active state
is a logic 1 or a rising edge. The normal IRQ pin has an active state that
is a logic 0 or a falling edge depending on the mask option.
If the mask option for edge- and level-sensitive interrupts and the mask
option for port A interrupts are both used, the presence of a logic 1 on
any one of the lower four port A pins causes an IRQ interrupt request. If
the mask option for edge-sensitive-only interrupts and the mask option
for port A interrupts are both used, the occurrence of a rising edge on
any one of the PA0–PA3 pins causes an IRQ interrupt request, as long
as the other PA0–PA3 pins are at a low level. As long as any one of the
PA0–PA3 IRQ inputs remains at a logic 1 level, or the IRQ remains at a
logic 0 level, the other PA0–PA3 IRQ inputs are effectively ignored. Port
Address:
$0010
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
PDIA7
PDIA6
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-2. Port A Pulldown Inhibit Register (PDRA)
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