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參數(shù)資料
| 型號： | GS9025 |
| 英文描述： | GENLINX II Serial Digital Receiver |
| 中文描述： | GENLINX二串行數(shù)字接收機 |
| 文件頁數(shù)： | 18/30頁 |
| 文件大?。?/td> | 445K |
| 代理商： | GS9025 |
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5.1 I2C Serial Interface
The I
2
C interface consists of a bi-directional serial data pin
(SDA) and a serial clock input pin (SCL). In addition, 3
input pins, A[2:0] are provided to assign the chip one of
eight possible I
2
C addresses (0001A
2
A
1
A
0
).
During an I
2
C write operation, the first byte written to the
chip (after the device has been addressed) is interpreted
as the starting HOSTIF write table address for the
communication. The next byte is interpreted as data to be
written to this address. The address then automatically
increments so that the following bytes are written to
subsequent addresses.
When executing a read operation, a write must be
performed first to load the starting address. After this, bytes
read from the chip will begin at this address and will auto-
increment.
If
the
read
communication with the chip is later established for another
read, the chip will resume reading at the next HOSTIF
memory address.
operation
is
halted
and
In I
2
C mode, P[7:5] and A/D must be set LOW while R/W
and CS must be set HIGH.
5.2 Parallel Interface
The asynchronous parallel interface consists of an 8-bit
multiplexed address/data bus (P[7:0]), a chip select pin
(CS), a read/write pin (R/W), and an address/data pin (A/D).
The following should be noted when interfacing to the
parallel port:
A) Read/Write cycles via the parallel interface are
completely independent and asynchronous to the
parallel clock PCLKOUT.
B) Signals are "strobed" into/out of the parallel port on the
falling edge of the CS signal. Setup and hold times, as
defined in the AC timing tables, are relative to this edge
and must be met (see Figure 14a)
C) The GS9020A drives the P[7:0] bus when the R/W pin is
HIGH and the CS pin is LOW. At all other times, the
P[7:0] port is in a high impedance state. The host
interface enable and disable times are shown in Figure
14b and are specified in the AC timing information. In
this figure, the rising/falling edges of R/W and CS are
not aligned to illustrate that the state of the P[7:0] I/Os is
only a combinatorial function of the R/W and CS pins.
A write cycle to the parallel interface is shown in Figure 14c.
The starting address of the operation is written to the chip
by putting the R/W pin LOW (indicating write) and the A/D
pin high (indicating ADDRESS). At t
0
, the falling edge of CS
strobes in the information. Following this, the A/D line
should be asserted LOW indicating data. The R/W line
remains LOW indicating a write operation and at t
1
the data
is strobed into the device.
A read example follows the write cycle. Note that the read
cycle begins with a write operation to indicate the starting
address. At t
2
, R/W is LOW (indicating write), A/D is HIGH
(indicating address) and P[7:0] represent the starting
address for the read cycle. After sufficient hold time, the
microcontroller releases the P[7:0] bus and the R/W is
asserted HIGH to indicate a read operation. At t
3
, the CS is
asserted low causing the GS9020A to present the required
data on the P[7:0] bus.
If two consecutive data read or write operations are
performed, the device will automatically increment the
address. However, for a completely random-access
operation, the address can be specified prior to every data
read or write operation.
5.3 Host Interface Read/Write Timing
Figure 15 illustrates valid times for reading/writing
information from the HOSTIF tables. It represents two fields
of video data entering and exiting the GS9020A. The
relative position of the EDH packet in the data stream is
also shown. (Note that the EDH packet entering the device
at t
0
, EDH F0, represents the EDH information from the
previous field, FIELD 0).
It is safe to read or write EDH information at least two lines
after an EDH packet exits the chip but before the
subsequent EDH packet enters the chip. Reading during
the time interval shown will show values from EDH F0.
Writing during the time interval shown will affect EDH F1.
Note that the above read/write timing should also be
observed when reading/writing flag information via the
FLAG PORT.
PIN
LOGIC OPR
HOST BIT
SCL
SDA
A[2:0]
PIN
LOGIC OPR
HOST BIT
P[7:0]
A/D
R/W
CS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9025 44PQFP | 制造商:Gennum Corporation 功能描述: |
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| GS9025A_05 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Serial Digital Receiver |
| GS9025ACQM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
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