參數(shù)資料
型號(hào)： GS8182T36BGD-333IT
廠商： GSI TECHNOLOGY
元件分類(lèi)： SRAM
英文描述： 512K X 36 DDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù)： 8/37頁(yè)
文件大?。?/td> 562K
代理商： GS8182T36BGD-333IT
GS8182T08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 6/2010
16/37
2007, GSI Technology
HSTL I/O DC Input Characteristics
Parameter
Symbol
Min
Max
Units
Notes
DC Input Logic High
VIH (dc)
VREF + 0.10
VDDQ + 0.3 V
V
1, 4
DC Input Logic Low
VIL (dc)
–0.3 V
VREF – 0.10
V
1, 3
Notes:
1. Compatible with both 1.8 V and 1.5 V I/O drivers.
2. These are DC test criteria. DC design criteria is VREF ± 50 mV. The AC VIH/VIL levels are defined separately for measuring timing
parameters.
3. VIL (Min) DC = –0.3 V, VIL(Min) AC = –1.5 V (pulse width ≤ 3 ns).
4. VIH (Max) DC = VDDQ + 0.3 V, VIH(Max) AC = VDDQ + 0.85 V (pulse width ≤ 3 ns).
HSTL I/O AC Input Characteristics
Parameter
Symbol
Min
Max
Units
Notes
AC Input Logic High
VIH (ac)
VREF + 0.20
—
V
2, 3
AC Input Logic Low
VIL (ac)
—
VREF – 0.20
V
2, 3
VREF Peak-to-Peak AC Voltage
VREF (ac)
—
5% VREF (DC)
V
1
Notes:
1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other.
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
20% tKHKH
VSS – 1.0 V
50%
VSS
VIH
Undershoot Measurement and Timing
Overshoot Measurement and Timing
20% tKHKH
VDD + 1.0 V
50%
VDD
VIL
Capacitance
oC, f = 1 MHZ, V
DD = 3.3 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0 V
4
5
pF
Output Capacitance
COUT
VOUT = 0 V
6
7
pF
Clock Capacitance
CCLK
—
5
6
pF
Note:
This parameter is sample tested.
(TA = 25
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