參數(shù)資料
型號(hào)： GS8182T36BGD-333IT
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 512K X 36 DDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù)： 13/37頁(yè)
文件大?。?/td> 562K
代理商： GS8182T36BGD-333IT
GS8182T08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 6/2010
20/37
2007, GSI Technology
AC Electrical Characteristics
Parameter
Symbol
-400
-375
-333
-300
-250
-200
-167
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Clock
K, K Clock Cycle Time
C, C Clock Cycle Time
tKHKH
tCHCH
2.5
8.4
2.67
8.4
3.0
8.4
3.3
8.4
4.0
8.4
5.0
8.4
6.0
8.4
ns
tTKC Variable
tKCVar
—
0.2
—
0.2
—
0.2
—
0.2
—
0.2
—
0.2
—
0.2
ns
6
K, K Clock High Pulse Width
C, C Clock High Pulse Width
tKHKL
tCHCL
1.0
—
1.13
—
1.2
—
1.32
—
1.6
—
2.0
—
2.4
—
ns
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
tKLKH
tCLCH
1.0
—
1.13
—
1.2
—
1.32
—
1.6
—
2.0
—
2.4
—
ns
K to K High
C to C High
tKHKH
tCHCH
1.0
—
1.13
—
1.35
—
1.49
—
1.8
—
2.2
—
2.7
—
ns
K to K High
C to C High
tKHKH
tCHCH
1.0
—
1.13
—
1.35
—
1.49
—
1.8
—
2.2
—
2.7
—
ns
K, K Clock High to C, C Clock High
tKHCH
0
1.1
0
1.2
0
1.3
0
1.45
0
1.8
0
2.3
0
2.8
ns
DLL Lock Time
tKCLock
1024
—
1024
—
1024
—
1024
—
1024
—
1024
—
1024
—
cy
cle
6
K Static to DLL reset
tKCReset
30
—
30
—
30
—
30
—
30
—
30
—
30
—
ns
Output Times
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
tKHQV
tCHQV
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
—
0.5
ns
4
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
tKHQX
tCHQX
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.5
—
ns
4
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid
tKHCQV
tCHCQV
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
—
0.5
ns
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold
tKHCQX
tCHCQX
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.5
—
ns
CQ, CQ High Output Valid
tCQHQV
—
0.25
—
0.25
—
0.25
—
0.27
—
0.30
—
0.35
—
0.40
ns
8
CQ, CQ High Output Hold
tCQHQX
–0.25
—
–0.25
—
–0.25
—
–0.27
—
–0.30
—
–0.35
—
–0.40
—
ns
8
CQ Phase Distortion
tCQHCQH
0.9
—
1.0
—
1.10
—
1.24
—
1.55
—
1.95
—
2.45
—
ns
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
tKHQZ
tCHQZ
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
—
0.5
ns
4
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
tKHQX1
tCHQX1
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.5
—
ns
4
Setup Times
Address Input Setup Time
tAVKH
0.4
—
0.4
—
0.4
—
0.4
—
0.5
—
0.6
—
0.7
—
ns
1
Control Input Setup Time (R/W, LD)
tIVKH
0.4
—
0.4
—
0.4
—
0.4
—
0.5
—
0.6
—
0.7
—
ns
2
Control Input Setup Time (BWX,
NWX)
tIVKH
0.28
—
0.28
—
0.28
—
0.3
—
0.35
—
0.4
—
0.5
—
ns
3
Data Input Setup Time
tDVKH
0.28
—
0.28
—
0.28
—
0.3
—
0.35
—
0.4
—
0.5
—
ns
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