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參數(shù)資料
| 型號： | GF9101-CMQ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Multirate Digital Filter |
| 中文描述： | 高性能多速率數(shù)字濾波器 |
| 文件頁數(shù)： | 6/23頁 |
| 文件大小： | 188K |
| 代理商： | GF9101-CMQ |
520 - 64 - 7
6
G
need to be loaded into the internal RAM. If location 0 is
used for filtering, MB0 > MB5 must be loaded for this
location. The example shown in Figure 2 loads the value
BB
H
into TEMP_REG_A.
Fig. 2 Microprocessor Loading Timing Diagram
SERIAL LOADING
Serial loading is sequential and synchronous. If serial
loading is selected the GF9101 will not enter the run mode
until the entire serial load sequence is completed at which
time the S_LOAD_CMP signal will go high. A bit will be
written each time LOAD_EN is low and COEF_WR makes a
high to low transition. Once the GF9101 is configured for
serial loading, 24 x 108 x 6 =15552 bits must be written
before the run mode is entered automatically. The 15552
bits must be entered in the order defined in Table 6. MB0 is
loaded first from RAM location 0 starting to fill the first 12
bits of tap 2. MB5 RAM location 107, tap 11 is loaded last.
When
S_LOAD_CMP will go high and the run mode will be active.
Below is a serial loading timing diagram. This example
shows the serial loading start-up sequence. Notice that the
falling edge of COEF_WR is used to register the serial data.
The frequency of COEF_WR should be
≤
1/4 CLK_IN
frequency.
the
serial
load
sequence
is
completed,
TABLE 6: Serial Mode Loading Order
Fig. 3 Serial Mode Timing Diagram
300
H
LOAD_EN
COEF_DATA
(7-0)
COEF-WR
BB
H
COEF_ADDR
(9-0)
Memory Bank 0
Memory Bank 1
Memory Bank 5
Ram
Location
TAP 2
TAP 1
TAP4
TAP 3
1,2,3 .... 12
13 ........ 24
2593 ............................. 2617
0,1,2 .... 11
0 .......... 11
0 .......... 11
0 .......... 11
25 .................................. 48
2618 ............................. 2642
0 .......... 11
0 .......... 11
0 .......... 11
0 .......... 11
2568 ............................. 2592
5160 ............................. 5184
0,1,2 .... 11
0 .......... 11
0 .......... 11
0 .......... 11
TAP12
TAP 11
5185 ............................. 5208
0 .......... 11
0 .......... 11
5209 ............................. 5233
0 .......... 11
0 .......... 11
15528 ...........................15552
0 .......... 11
0 .......... 11
0
1
107
.
.
.
.
.
.
.
.
.
.
COEF_DATA (7)
LOAD_EN
CLK_IN
CONFIGURE
S_LOAD_CMP
COEF_WR
BIT 2
BIT 1
BIT 3
BIT 15551
BIT 15552
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