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參數(shù)資料
| 型號： | GF9101-CMQ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Multirate Digital Filter |
| 中文描述： | 高性能多速率數(shù)字濾波器 |
| 文件頁數(shù)： | 13/23頁 |
| 文件大?。?/td> | 188K |
| 代理商： | GF9101-CMQ |
520 - 64 - 7
13
G
For the 48 tap filter, input data A
n
and coefficients C
n
are
shown in Figure 12. The pipelined output section of the 48
tap filter is shown in Figure 14. Note that two register delays
are introduced due to R2 and R3 between the accumulators
of device number 1 and number 2. An additional delay is
introduced when the filter-sum is fed back to be added to
the next sum by selecting FB_SEL_1. The timing diagram
for the 48 tap asymmetric filter is shown in Figure 15. The
processing clock runs at twice the data rate since the A and
B registers of the GF9101 are multiplexed internally..
Fig. 12 Input Data A
n
and Coefficients C
n
TABLE 11 Configuration Word for the Cascaded GF9101
’
s
DEVICE NO. 1
DEVICE NO. 2
BIT NO.
CONFIG.
WORD
CONFIG.
WORD
DESCRIPTION
0
1
1
Data A and B are both signed data.
1
1
1
2
0
0
1 clock cycle delay in device no. 1 and 4 clock delay in device no. 2
3
0
1
4
0
0
Using each device as 2 x 12 tap filters. Note that in device no. 2
DATA_A_OUT is externally connected to DATA_B_IN.
5
0
0
Assuming serial load mode selected for both devices.
6
0
0
C
4
C
5
C
6
C
36
C
38
C
40
C
3
C
2
C
1
C
0
C
41
C
44
C
43
C
39
C
42
C
45
C
46
C
7
C
37
C
47
A
47
A
11
A
45
A
4
A
5
A
40
A
41
A
42
A
43
A
3
A
1
A
0
A
46
A
9
A
10
A
44
A
8
A
7
A
6
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