參數(shù)資料
型號(hào)： GF9101-CMQ
廠商： Electronic Theatre Controls, Inc.
英文描述： High Performance Multirate Digital Filter
中文描述： 高性能多速率數(shù)字濾波器
文件頁(yè)數(shù)： 2/23頁(yè)
文件大?。?/td> 188K
代理商： GF9101-CMQ
520 - 64 - 7
2
G
I/O DESCRIPTION
SYMBOL
PIN NO.
TYPE
DESCRIPTION
V
DD
1, 10, 20, 29, 40, 41,
59, 69, 80, 81, 90, 99,
109, 120, 121, 129,
140, 150, 160
+5 V power supply pins. 0.1
μ
F capacitors between the V
CC
and GND pins
are recommended.
GND
3, 6, 8, 19, 33, 36, 39,
46, 49, 60, 73, 76, 79,
83, 86, 88, 100, 113,
116, 119, 122, 125,
139, 153, 155, 159
Device ground.
CLK_IN
138
I
System clock. All inputs except for CONFIGURE, and all internal registers are
clocked on the rising edge of CLK_IN.
DATA_A_IN (9-0)
127, 128, 130-137
I
Input data to registers A0 - A11. 9 bit signed or 10 bit unsigned data.
DATA_B_IN (9-0)
141-149, 151
I
Input data to registers B11 - B0. 9 bit signed or 10 bit unsigned data.
ENA
23
I
Shift enable for A0 - A11. Enables shifting of A registers when high.
ENB
24
I
Shift enable for B0 - B11. Enables shifting of B registers when high.
ENC
25
I
Enable for C0-C11. Enables C registers when high. The C registers transfer
data from either the A or B registers depending on the state of SEL_A/B.
SEL_A/B
22
I
Selects A or B registers. Selects registers A when high or registers B when
low to be transferred to the C registers.
COEF_DATA (7-0)
96-98, 101-105
I
Data bus for coefficients and configuration register:
a) Parallel and microprocessor loading modes : COEF_DATA (7-0) is used to
load 8 bit data into internal RAM.
b) Serial Loading mode: COEF_DATA (7) is used to serially load the internal
RAM.
c) Configuration mode: COEF_DATA (6-0) are inputs to the CONFIGURATION
register.
COEF_ADDR (9-0)
78, 77, 75, 74, 72, 47,
45-42
I
Address bus for internal RAM (address 0
—
> 107):
a) Run mode: COEF_ADDR (6-0) selects one of the 108 sets of 12 coefficients
in the internal RAM.
b) Parallel and micro-processor loading modes: Selects the internal RAM
address for the 8-bit data loading COEF_DATA (7-0).
COEF_WR
17
I
Enable for COEF_DATA (7-0). LOAD_EN must be enabled for COEF_WR to
work:
a) Parallel and micro-processor loading modes : Enables COEF_DATA (7-0)
registers or loading 8 bit data in internal RAM.
b) Serial Loading mode: On a high to low transition, a one bit data gets
clocked in to the internal RAM through COEF_DATA bit 7.
LOAD_EN
18
I
Used during loading mode. This signal selects a particular GF9101 device
when 2 or more share the same bus for loading. The particular GF9101
device is selected when set low. LOAD_EN must be enabled for COEF_WR.
For a single GF9101 using the serial loading, this pin can be set low.
NEGATE
126
I
This signal negates the filter sum before it enters the pipelined output section
when high.
ZERO
123
I
Zeros filter sum before it enters the pipelined output section when low.
FB_SEL
124
I
Feedback select. Selects data in PIPELINE_IN when low or filter sum in
PIPELINE_OUT when high to the input of the output accumulator.
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