520 - 64 - 7

15

G

Fig. 14 Pipelined Output Stages for Two Cascaded GF9101

’

s

Dedicated serial PROM's can be used to load the

coefficients into the internal RAM of each GF9101. Note that

when data is fed back into DATA_B_IN, it enters register

B12 of device number 2. Therefore, while loading the

coefficients into the internal RAM for the B registers the

coefficients should be arranged as shown in Table 12. If a

single source is used for coefficient loading, the LOAD_EN

signal is used to select the appropriate device. Also, the

S_LOAD_CMP signal can be used as an indicator for a

successful load.

Fig. 15 Timing Diagram for a 48 Tap Asymmetric Filter

TABLE 12: Internal RAM Address and Contents for a 48-tap Asymmetric Filter using Two Cascaded GF9101

’

s

COEF_ADDR

INTERNAL RAM CONTENTS

Device No. 1

Device No. 2

00

H

C0

—

> C11 (registers A1

—

> A12)

C12

—

> C23 (registers A1

—

> A12)

01

H

C47

—

> C36 (registers B1

—

> B12)

C35

—

> C24 (registers B1

—

> B12)

1

0

20

20

Σ

20

8

OFFSET [7..0]

R

R

4

1

0

20

FB

–

SEL-2

20

Σ

20

GF9101

FILTER

–

SUM 2

OUTPUT [11..0]

DEVICE No.2

R

R

2

FB

–

SEL-1

GF9101

FILTER

–

SUM 1

DEVICE No.1

R

1

20

20

20

12

R

3

DATA_A_IN

ZERO

LOAD_EN

CLK_IN

CONFIGURE

ENA

ENB

SEL_A/B

00

H

01

H

00

H

01

H

00

H

01

H

00

H

01

H

00

H

01

H

00

H

01

H

00

H

01

H

1 2 3 4 5 6 7 8 9 10 11 12 13 14

COEF_ADDR

(6-0)

FB_SEL-1

NEGATE

FB_SEL-2