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參數(shù)資料
| 型號： | GF9101-CMQ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Multirate Digital Filter |
| 中文描述： | 高性能多速率數(shù)字濾波器 |
| 文件頁數(shù)： | 5/23頁 |
| 文件大?。?/td> | 188K |
| 代理商： | GF9101-CMQ |
520 - 64 - 7
5
G
The timing diagram shown in Figure 1 loads the memories shown in Table 4:
Fig. 1 Parallel Loading Timing Diagram
The address generated is shown in Table 5.
Timing for the parallel loading signals is the same as that
for other synchronous inputs.
MICROPROCESSOR LOADING
If microprocessor loading is selected, the LOAD_EN pin
alone determines the run mode or the load mode. When
LOAD_EN is low, the load mode is selected, the run mode
is disabled, but a write will not occur until COEF_WR is low.
Microprocessor
asynchronous. Like parallel loading, microprocessor
loading uses COEF_DATA (7-0) and COEF_ADDR (9-0) to
write three 8-bit words for each 24-bit memory written.
Addressing is the same as for parallel loading. In
microprocessor mode, at least one set of filter coefficients
loading
is
random
access
and
TABLE 4: Memory Loaded into Internal RAM in Parallel Load Mode
TAP (location)
12-bit WORD IN HEX.
MEMORY BANK
1 (0)
FB2
MB0
2 (0)
EF4
MB0
11 (107)
CCC
MB5
12 (107)
DDD
MB5
COEF_DATA
(7-0)
COEF_WR
LOAD_EN
CLK_IN
CONFIGURE
COEF_ADDR
(9-0)
300
XX
F4
2E
FB
DD
CD
CC
XX
XX
2EB
3EB
36B
000
380
XX
TABLE 5: Address Generation for Parallel Loading Example
DESTINATION
COEF_ADDR
(9-7) IN BINARY
COEF_ADDR
(6-0) IN HEX
COEF_ADDR
(9-0) IN HEX
TEMP_REG_A
110
X
300
TEMP_REG_B
111
X
380
MB0
000
0
000
TEMP_REG_A
110
X
36B or 300
TEMP_REG_B
111
X
3EB or 380
MB5
101
6B
2EB
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