參數(shù)資料
型號: FW82801E
廠商: Intel Corp.
英文描述: Intel 82801E Communications I/O Controller Hub (C-ICH)
中文描述: 英特爾82801E通訊I / O控制器集線器(丙,出血)
文件頁數(shù): 70/84頁
文件大?。?/td> 1196K
代理商: FW82801E
Intel
82801E C-ICH
70
Advance Information Datasheet
4.5
Timing Diagrams
Table 55. Power Sequencing and Reset Signal Timings
Sym
Parameter
Min
Max
Units
Notes
Fig
t170
VccRTC active to RTCRST# inactive
5
-
ms
26
t171
VccRTC supply active to Vcc supplies active
0
-
ms
3
26
t172
V5Ref active to Vcc3_3, Vcc1_8 active
0
-
ms
1, 2
26, 27
t173
Vcc supplies active to PWROK, VRMPWRGD
active
10
-
ms
2
26, 27
t174
AC_RST# active low pulse width
1
μs
t175
AC_RST# inactive to BIT_CLK startup delay
162.8
ns
NOTES:
1. The V5Ref supply must power up before or simultaneous with its associated 3.3 V supply, and must power
down simultaneous with or after the 3.3V supply. See Section 3.3.4 for details.
2. The associated 3.3 V and 1.8 V supplies are assumed to power up or down together. The difference
between the levels of the 3.3 V and 1.8 V supplies must never be greater than 2.0V.
3. The Vcc supplies must
never
be active while the VccRTC supply is inactive.
Figure 9. Clock Timing
Figure 10. Valid Delay From Rising Clock Edge
2.0V
0.8V
Period
High Time
Low Time
Fall Time
Rise Time
Clock
1.5V
Valid Delay
VT
Output
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