- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375989 > FW82801E (Intel Corp.) Intel 82801E Communications I/O Controller Hub (C-ICH) PDF資料下載
參數(shù)資料
| 型號： | FW82801E |
| 廠商： | Intel Corp. |
| 英文描述： | Intel 82801E Communications I/O Controller Hub (C-ICH) |
| 中文描述： | 英特爾82801E通訊I / O控制器集線器（丙，出血） |
| 文件頁數(shù)： | 55/84頁 |
| 文件大?。?/td> | 1196K |
| 代理商： | FW82801E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁當前第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
Intel
82801E C-ICH
Advance Information Datasheet
55
3.4.5
Power Planes for Input Signals
Table 33 shows the power plane associated with each input signal, as well as what device drives the
signal at various times. Valid states include:
High
Low
Static: Will be high or low, but will not change
Driven: Will be high or low, and is allowed to change
Running: For input clocks
STPCLK#
CPU I/O
PCIRST#
High
High
SMBus Interface
SMBCLK, SMBDATA
Main I/O
RSMRST#
High-Z
High-Z
System Management Interface
SMLINK[1:0]
Main I/O
RSMRST#
High-Z
High-Z
Miscellaneous Signals
SPKR
Main I/O
PCIRST#
High-Z with
internal pull-up
Low
SUSCLK
Main I/O
RSMRST#
Running
Unmuxed GPIO Signals
GPIO[18]
Main I/O
PCIRST#
High
See Note 2
GPIO[19:20]
Main I/O
PCIRST#
High
High
GPIO[21]
Main I/O
PCIRST#
High
High
GPIO[22]
Main I/O
PCIRST#
High-Z
High-Z
GPIO[23]
Main I/O
PCIRST#
Low
Low
GPIO[24]
Main I/O
RSMRST#
High-Z
High
GPIO[25]
Main I/O
RSMRST#
High-Z
High
GPIO[27:28]
Main I/O
RSMRST#
HIgh-Z
High
Table 32. Power Plane and States for Output and I/O Signals (Sheet 3 of 3)
Signal Name
Power Plane
Reset Signal
During Reset
Immediately
after Reset
NOTES:
1. The 82801E C-ICH sets these signals at reset for processor frequency strap.
2. I GPIO[18] will toggle at a frequency of approximately 1 Hz when the 82801E C-ICH comes out of reset
3. CPUPWRGD is an open-drain output that represents a logical AND of the VRMPWRGD and PWROK
signals and, thus, are driven low by 82801E C-ICH when either VRMPWRGD or PWROK are inactive.
During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low
to High-Z.
4. GPIO[24:25, 27:28]: These signals remain tri-stated for up to 110 ms after RSMRST# deassertion. At this
point, they will be driven to their default (High) state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FWB150 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB151 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB1510 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB152 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB154 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82801E S L5AW | 制造商:Intel 功能描述:I/O Controller Phase Controller 421-Pin BGA |
| FW82801EB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| FW82801EB S L6TN | 制造商:Intel 功能描述:CONTROLLER: IO CONTROLLER |
| FW82801EB S L73Z | 制造商:Intel 功能描述:I/O Controller Phase Controller 460-Pin BGA |
| FW82801ER | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。