參數(shù)資料
型號: FW82801E
廠商: Intel Corp.
英文描述: Intel 82801E Communications I/O Controller Hub (C-ICH)
中文描述: 英特爾82801E通訊I / O控制器集線器(丙,出血)
文件頁數(shù): 69/84頁
文件大?。?/td> 1196K
代理商: FW82801E
Intel
82801E C-ICH
Advance Information Datasheet
69
Table 52. UART Timings
Sym
Parameter
Min
Max
Units
Notes
Fig
t150a
SIU0_TXD, SIU1_TXD Valid Delay from UART_CLK Rising
2
13
ns
10
t150a
SIU0_DTR#, SIU0_RTS#, SIU1_DTR#, and SIU1_RTS# Valid
Delay from SIU_LCLK Rising
2
11
ns
10
t153a
SIU0_RXD, SIU0_CTS#, SIU0_DSR#, SIU0_DCD#,
SIU0_RI# SIU1_RXD, SIU1_CTS#, SIU1_DSR#,
SIU1_DCD#, and SIU1_RI# Setup Time to SIU_LCLK Rising
7
ns
11
t154a
SIU0_RXD, SIU0_CTS#, SIU0_DSR#, SIU0_DCD#,
SIU0_RI#, SIU1_RXD, SIU1_CTS#, SIU1_DSR#,
SIU1_DCD#, and SIU1_RI# Hold Time from SIU_LCLK Rising
0
ns
11
t10a
SIU0_CTS#, SIU0_DSR#, SIU0_DCD#, SIU0_RI#,
SIU1_CTS#, SIU1_DSR#, SIU1_DCD#, and SIU1_RI#
high time
100
9
t11a
SIU0_CTS#, SIU0_DSR#, SIU0_DCD#, SIU0_RI#,
SIU1_CTS#, SIU1_DSR#, SIU1_DCD#, and SIU1_RI#
low time
100
9
Table 53. LPC Timing
Sym
Parameter
Min
Max
Units
Notes
Fig
t150
LAD[3:0] Valid Delay from PCICLK Rising
2
11
ns
10
t151
LAD[3:0] Output Enable Delay from PCICLK Rising
2
ns
14
t152
LAD[3:0] Float Delay from PCICLK Rising
28
ns
12
t153
LAD[3:0] Setup Time to PCICLK Rising
7
ns
11
t154
LAD[3:0] Hold Time from PCICLK Rising
0
ns
11
t155
LDRQ[1:0]# Setup Time to PCICLK Rising
12
ns
11
t156
LDRQ[1:0]# Hold Time from PCICLK Rising
0
ns
11
t157
LFRAME# Valid Delay from PCICLK Rising
2
12
ns
10
Table 54. Miscellaneous Timings
Sym
Parameter
Min
Max
Units
Notes
Fig
t160
SERIRQ Setup Time to PCICLK Rising
7
ns
11
t161
SERIRQ Hold Time from PCICLK Rising
0
ns
11
t162
RI#, EXTSMI#, GPI, USB Resume Pulse Width
2
RTCCLK
13
t163
SPKR Valid Delay from OSC Rising
200
ns
10
t164
SERR# Active to NMI Active
200
ns
t165
IGNNE# Inactive from FERR# Inactive
230
ns
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