Contents
6
Advance Information Datasheet
50
51
52
53
54
55
56
57
58
59
60
61
62
SMBus Timing ............................................................................................................................68
SIU LPC and Serial IRQ Timings ...............................................................................................68
UART Timings ............................................................................................................................69
LPC Timing.................................................................................................................................69
Miscellaneous Timings ...............................................................................................................69
Power Sequencing and Reset Signal Timings ...........................................................................70
Test Mode Selection...................................................................................................................77
XOR Chain #1 ............................................................................................................................79
XOR Chain #2; Chain 2-1 and Chain 2-2 ...................................................................................80
XOR Chain #3; Chain 3-1 and Chain 3-2 ...................................................................................81
XOR Chain #4; Chain 4-1 and Chain 4-2 ...................................................................................82
Signals Not in XOR Chain ..........................................................................................................83
XOR Test Pattern Example ........................................................................................................84
Revision History
Date
Revision
Description
January 2001
003
Corrected XOR Chain 2. Added note to CPUSLP# signal
description.
December 2001
002
Corrected pinouts and pin list.
December 2001
001
First release of this datasheet.