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參數(shù)資料
| 型號： | FW82801E |
| 廠商： | Intel Corp. |
| 英文描述： | Intel 82801E Communications I/O Controller Hub (C-ICH) |
| 中文描述： | 英特爾82801E通訊I / O控制器集線器（丙，出血） |
| 文件頁數(shù)： | 49/84頁 |
| 文件大?。?/td> | 1196K |
| 代理商： | FW82801E |
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Intel
82801E C-ICH
Advance Information Datasheet
49
3.3
Pin Straps
3.3.1
Functional Straps
The following signals are used for static configuration. They are sampled at the rising edge of
PWROK to select configurations and then revert later to their normal usage. To invoke the
associated mode, the signal should be driven at least four PCI clocks prior to the time it is sampled.
3.3.2
Test Signals
3.3.2.1
Test Mode Selection
When PWROK is active (high), driving RTCRST# low for a number of PCI clocks (33 MHz) will
activate a particular test mode as specified in Table 28.
Note:
RTCRST# may be driven low any time after PCIRST is inactive. Refer to
“Testability” on page 77
for a detailed description of the 82801E C-ICH test modes.
Table 27. Functional Strap Definitions
Signal
Usage
When
Sampled
Comment
EE0_DOUT,
EE1_DOUT
Reserved
System designers should include a placeholder for a pull-down
resistor on EEn_DOUT but do not populate the resistor
GNT[A]#
Top-Swap
Override
Rising
Edge of
PWROK
The signal has a weak internal pull-up. If the signal is sampled low,
the system is strapped to the “Top-Swap” mode (82801E C-ICH will
invert A16 for all cycles targeting FWH BIOS space). The status of this
strap is readable via the Top-Swap bit (bit 13, D31: F0, Offset D4h).
Note that software will not be able to clear the Top-Swap bit until the
system is rebooted without GNT[A]# being pulled down.
HLCOMP
Enhanced
Hub
Interface
Mode
During
PCIRST#
assertion
If this signal is sampled high (via an external pull-up to VCC1_8), the
normal hub interface buffer mode will be selected. If this signal is
sampled low (via an external pull-down), the enhanced hub interface
buffer mode will be selected.
See the specific platform design guide for resistor values and routing
guidelines for each hub interface mode.
SPKR
No Reboot
Rising
Edge of
PWROK
The signal has a weak internal pull-up. If the signal is sampled low,
the system is strapped to the “No Reboot” mode (82801E C-ICH will
disable the TCO Timer system reboot feature). The status of this strap
is readable via the NO_REBOOT bit (bit 1, D31: F0, Offset D4h).
Table 28. Test Mode Selection
Number of PCI Clocks RTCRST# driven low after PWROK active
Test Mode
<4
No Test Mode Selected
4
XOR Chain 1
5
XOR Chain 2
6
XOR Chain 3
7
XOR Chain 4
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