- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375989 > FW82801E (Intel Corp.) Intel 82801E Communications I/O Controller Hub (C-ICH) PDF資料下載
參數(shù)資料
| 型號： | FW82801E |
| 廠商： | Intel Corp. |
| 英文描述： | Intel 82801E Communications I/O Controller Hub (C-ICH) |
| 中文描述： | 英特爾82801E通訊I / O控制器集線器（丙，出血） |
| 文件頁數(shù)： | 43/84頁 |
| 文件大小： | 1196K |
| 代理商： | FW82801E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁當前第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
Intel
82801E C-ICH
Advance Information Datasheet
43
3.2.11
Processor Interface
Table 17. Processor Interface Signals (Sheet 1 of 2)
Name
Type
Description
A20M#
O
Mask A20:
A20M# goes active based on setting the appropriate bit in the Port 92h
register, or based on the A20GATE signal.
Speed Strap:
During the reset sequence, 82801E C-ICH drives A20M# high if the
corresponding bit is set in the FREQ_STRP register.
CPUSLP#
O
Processor Sleep:
This signal puts the processor into a state that saves
substantial power compared to Stop-Grant state. However, during that time, no
snoops occur. The 82801E C-ICH can optionally assert the CPUSLP# signal when
going to the S1 state.
NOTE:
The 82801E C-ICH does not support Sleep states. This signal must be
pulled up through an 8.2 K
resistor to 3.3 V.
FERR#
I
Numeric Coprocessor Error:
This signal is tied to the coprocessor error signal
on the processor. FERR# is only used if the 82801E C-ICH coprocessor error
reporting function is enabled in the General Control Register (Device 31:Function
0, Offset D0, bit 13). If FERR# is asserted, the 82801E C-ICH generates an
internal IRQ13 to its interrupt controller unit. It is also used to gate the IGNNE#
signal to ensure that IGNNE# is not asserted to the processor unless FERR# is
active. FERR# requires an external weak pull-up to ensure a high level when the
coprocessor error function is disabled.
IGNNE#
O
Ignore Numeric Error:
This signal is connected to the ignore error pin on the
processor. IGNNE# is only used if the 82801E C-ICH coprocessor error reporting
function is enabled in the General Control Register (Device 31:Function 0, Offset
D0, bit 13). If FERR# is active, indicating a coprocessor error, a write to the
Coprocessor Error Register (F0h) causes the IGNNE# to be asserted. IGNNE#
remains asserted until FERR# is negated. If FERR# is not asserted when the
Coprocessor Error Register is written, the IGNNE# signal is not asserted.
Speed Strap:
During the reset sequence, 82801E C-ICH drives IGNNE# high if
the corresponding bit is set in the FREQ_STRP register.
INIT#
O
Initialization:
INIT# is asserted by the 82801E C-ICH for 16 PCI clocks to reset
the processor. 82801E C-ICH can be configured to support processor BIST. In that
case, INIT# will be active when PCIRST# is active.
INTR
O
Processor Interrupt:
INTR is asserted by the 82801E C-ICH to signal the
processor that an interrupt request is pending and needs to be serviced. It is an
asynchronous output and normally driven low.
Speed Strap:
During the reset sequence, 82801E C-ICH drives INTR high if the
corresponding bit is set in the FREQ_STRP register.
NMI
O
Non-Maskable Interrupt:
NMI is used to force a non-maskable interrupt to the
processor. The 82801E C-ICH can generate an NMI when either SERR# or
IOCHK# is asserted. The processor detects an NMI when it detects a rising edge
on NMI. NMI is reset by setting the corresponding NMI source enable/disable bit in
the NMI Status and Control Register.
Speed Strap:
During the reset sequence, 82801E C-ICH drives NMI high if the
corresponding bit is set in the FREQ_STRP register.
SMI#
O
System Management Interrupt:
SMI# is an active low output synchronous to
PCICLK. It is asserted by the 82801E C-ICH in response to one of many enabled
hardware or software events.
STPCLK#
O
Stop Clock Request:
STPCLK# is an active low output synchronous to PCICLK.
It is asserted by the 82801E C-ICH in response to one of many hardware or
software events. When the processor samples STPCLK# asserted, it responds by
stopping its internal clock.
相關PDF資料 |
PDF描述 |
|---|---|
| FWB150 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB151 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB1510 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB152 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB154 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| FW82801E S L5AW | 制造商:Intel 功能描述:I/O Controller Phase Controller 421-Pin BGA |
| FW82801EB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| FW82801EB S L6TN | 制造商:Intel 功能描述:CONTROLLER: IO CONTROLLER |
| FW82801EB S L73Z | 制造商:Intel 功能描述:I/O Controller Phase Controller 460-Pin BGA |
| FW82801ER | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。