參數資料
型號： FW82801E
廠商： Intel Corp.
英文描述： Intel 82801E Communications I/O Controller Hub (C-ICH)
中文描述： 英特爾82801E通訊I / O控制器集線器（丙，出血）
文件頁數： 64/84頁
文件大?。?/td> 1196K
代理商： FW82801E
Intel
82801E C-ICH
64
Advance Information Datasheet
t45
C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,
PERR#, PLOCK#, DEVSEL#, GNT[A:B]# Float
Delay from PCICLK Rising
2
28
ns
12
t46
C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,
SERR#, PERR#, DEVSEL#, Setup Time to
PCICLK Rising
7
ns
11
t47
C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,
SERR#, PERR#, DEVSEL#, REQ[A:B]# Hold
Time from PCLKIN Rising
0
ns
11
t48
PCIRST# Low Pulse Width
1
ms
13
t49
GNT[A:B}#, GNT[5, 3:0]# Valid Delay from
PCICLK Rising
2
12
ns
t50
REQ[A:B]#, REQ[5, 3:0]# Setup Timer to PCICLK
Rising
12
ns
Table 45. IDE PIO & Multiword DMA Mode Timing (Sheet 1 of 2)
Sym
Parameter
Min
Max
Units
Notes
Figure
t60
PDIOR#/PDIOW#/SDIOR#/SDIOW# Active From
CLK66 Rising
2
20
ns
15, 16
t61
PDIOR#/PDIOW#/SDIOR#/SDIOW# Inactive From
CLK66 Rising
2
20
ns
15, 16
t62
PDA[2:0]/SDA[2:0] Valid Delay From CLK66 Rising
2
30
ns
15
t63
PDCS1#/SDCS1#, PDCS3#/SDCS3# Active From
CLK66 Rising
2
30
ns
15
t64
PDCS1#/SDCS1#, PDCS3#/SDCS3# Inactive From
CLK66 Rising
2
30
ns
15
t65
PDDACK#/SDDACK# Active From CLK66 Rising
2
20
ns
16
t66
PDDACK#/SDDACK# Inactive From CLK66 Rising
2
20
ns
t67
PDDREQ/SDDREQ Setup Time to CLK66 Rising
7
ns
16
t68
PDDREQ/SDDREQ Hold From CLK66 Rising
7
ns
16
t69
PDD[15:0]/SDD[15:0] Valid Delay From CLK66
Rising
2
30
ns
15, 16
t70
PDD[15:0]/SDD[15:0] Setup Time to CLK66 Rising
10
ns
15, 16
t71
PDD[15:0]/SDD[15:0] Hold From CLK66 Rising
7
ns
15, 16
t72
PIORDY/SIORDY Setup Time to CLK66 Rising
7
ns
1
15
t73
PIORDY/SIORDY Hold From CLK66 Rising
7
ns
1
15
NOTES:
1. IORDY is internally synchronized. This timing is to guarantee recognition on the next clock.
2. PIORDY sample point from DIOx# assertion and PDIOx# active pulse width is programmable from 2-5 PCI
clocks when the drive mode is Mode 2 or greater. Refer to the ISP field in the IDE Timing Register
3. PIORDY sample point from DIOx# assertion, PDIOx# active pulse width and PDIOx# inactive pulse width
cycle time is the compatible timing when the drive mode is Mode 0/1. Refer to the TIM0/1 field in the IDE
timing register.
4. PDIOx# inactive pulse width is programmable from 1-4 PCI clocks when the drive mode is Mode 2 or
greater. Refer to the RCT field in the IDE Timing Register.
Table 44. PCI Interface Timing (Sheet 2 of 2)
Sym
Parameter
Min
Max
Units
Notes
Figure
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