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參數(shù)資料
| 型號： | FTS64K |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | 50/MDR/RECP/VERT PRS FIT/M2.6/SCW/30 MIN |
| 中文描述： | 64K的快閃記憶體字節(jié) |
| 文件頁數(shù)： | 30/44頁 |
| 文件大小： | 401K |
| 代理商： | FTS64K |
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FTS64K Block User Guide — Version V01.00
30
WARNING
Because of the impact of clock synchronization on the accuracy of the functional timings,
programming or erasing the Flash cannot be performed if the bus clock runs at less than 1 MHz.
Programming or erasing the Flash with an input clock < 150kHz should be avoided. Setting
FCLKDIV to a value such that FCLK < 150kHz can destroy the Flash due to overstress. Setting
FCLKDIV to a value such that (1/FCLK+Tbus) < 5
μ
s can result in incomplete programming or
erasure of the memory array cells.
If the FCLKDIV register is written, the bit FDIVLD is set automatically. If this bit is zero, the register has
not been written since the last reset. Program and erase commands will not be executed if this register has
not been written to.
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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