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| 型號： | FTS64K |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 50/MDR/RECP/VERT PRS FIT/M2.6/SCW/30 MIN |
| 中文描述： | 64K的快閃記憶體字節(jié) |
| 文件頁數(shù)： | 22/44頁 |
| 文件大小： | 401K |
| 代理商： | FTS64K |
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FTS64K Block User Guide — Version V01.00
22
3.3.4 FCNFG — Flash Configuration Register
The FCNFG register enables the Flash interrupts and gates the security backdoor writes.
Figure 3-5 Flash Configuration Register (FCNFG)
CBEIE, CCIE and KEYACC are readable and writable. Bits 4-0 read zero and are not writable.
CBEIE — Command Buffer Empty Interrupt Enable.
The CBEIE bit enables the interrupts in case of an empty command buffer in the Flash.
1 = An interrupt will be requested whenever the CBEIF flag,
Figure 3-7
, is set.
0 = Command Buffer Empty interrupts disabled.
CCIE — Command Complete Interrupt Enable.
The CCIE bit enables the interrupts in case of all commands being completed in the Flash.
1 = An interrupt will be requested whenever the CCIF,
Figure 3-7
, flag is set.
0 = Command Complete interrupts disabled.
KEYACC — Enable Security Key Writing.
1 = Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array
return invalid data.
0 = Flash writes are interpreted as the start of a program or erase sequence.
3.3.5 FPROT — Flash Protection Register
The FPROT register defines which Flash sectors are protected against program or erase.
Figure 3-6 Flash Protection Register (FPROT)
Register address BASE + $103
7
R
CBEIE
W
Reset:
0
6
5
4
0
3
0
2
0
1
0
0
0
CCIE
KEYACC
0
0
0
0
0
0
0
= Unimplemented or Reserved
Register address BASE + $104
7
R
FPOPEN
W
Reset:
F
6
5
4
3
2
1
0
NV6
FPHDIS
FPHS1
FPHS0
FPLDIS
FPLS1
FPLS0
F
F
F
F
F
F
F
= Unimplemented or Reserved
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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