參數(shù)資料
型號(hào)： FTS64K
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 50/MDR/RECP/VERT PRS FIT/M2.6/SCW/30 MIN
中文描述： 64K的快閃記憶體字節(jié)
文件頁(yè)數(shù)： 29/44頁(yè)
文件大?。?/td> 401K
代理商： FTS64K
29
Section 4 Functional Description
4.1 Program and Erase Operation
Write and read operations are both used for the program and erase algorithms described in this section.
These algorithms are controlled by a state machine whose timebase FCLK is derived from the oscillator
clock via a programmable divider. The command register as well as the associated address and data
registersoperateasabufferandaregister(2-stageFIFO),sothatanewcommandalongwiththenecessary
dataandaddresscanbestoredtothebufferwhilethepreviouscommandisstillinprogress.Thispipelined
operationallowsatimeoptimizationwhenprogrammingmorethanonewordonaspecificrow,asthehigh
voltage generation can be kept ON in between two programming commands. The pipelined operation also
allowsasimplificationofcommandlaunching.Bufferemptyaswellascommandcompletionaresignalled
by flags in the Flash status register. Interrupts for the Flash will be generated if enabled.
The next four subsections describe:
How to write the FCLKDIV register.
The write sequences used to program, erase and erase-verify the Flash.
Valid Flash commands.
Errors resulting from illegal Flash operations.
4.1.1 Writing the FCLKDIV Register
Prior to issuing any program or erase command, it is first necessary to write the FCLKDIV register to
divide the oscillator down to within the 150kHz to 200kHz range. The program and erase timings are also
afunctionofthebusclock,suchthattheFCLKDIVdeterminationmusttakethisinformationintoaccount.
If we define:
FCLK as the clock of the Flash timing control block
Tbus as the period of the bus clock
INT(x) as taking the integer part of x (e.g. INT(4.323)=4),
then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in
Figure 4-1
.
For example, if the oscillator clock frequency is 950kHz and the bus clock is 10MHz, FCLKDIV bits
FDIV[5:0] should be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK is then 190kHz. As
a result, the Flash algorithm timings are increased over optimum target by:
NOTE
Command execution time will increase proportionally with the period of FCLK.
200
190
–
(
)
200
100
×
5%
=
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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