參數(shù)資料
型號(hào)： FS7VS-5
廠商： Mitsubishi Electric Corporation
英文描述： HIGH-SPEED SWITCHING USE
中文描述： 高速開關(guān)使用
文件頁數(shù)： 33/91頁
文件大?。?/td> 488K
代理商： FS7VS-5
PSD9XX Family
PSD935G2
32
The
PSD935G2
Functional
Blocks
(cont.)
9.2 PLDs
The PLDs bring programmable logic functionality to the PSD935G2. After specifying the
logic for the PLDs in PSDsoft, the logic is programmed into the device and available upon
power-up.
The PSD935G2 contains two PLDs: the Decode PLD (DPLD), and the General Purpose
PLD (GPLD). The PLDs are briefly discussed in the next few paragraphs, and in more
detail in sections 9.2.1 and 9.2.2. Figure 11 shows the configuration of the PLDs.
The DPLD performs address decoding for internal components, such as memory,
registers, and I/O port selects.
The GPLD can be used to generate external chip selects, control signals or logic functions.
The GPLD has 24 outputs that are connected to Port A, B and C.
The AND array is used to form product terms. These product terms are specified using
PSDsoft. An Input Bus consisting of 66 signals is connected to the PLDs. The signals are
shown in Table 12. The complement of the 66 signals are also available as inputs to the
AND array.
Input Source
Input Name
Number
of Signals
MCU Address Bus
MCU Control Signals
Reset
Power Down
Port A Input
Port B Input
Port C Input
Port D Inputs
Port F Inputs
Page Register
Flash Programming Status Bit
A[15:0]
*
CNTL[2:0]
RST
PDN
PA[7-0]
PB[7-0]
PC[7-0]
PD[3:0]
PF[7:0]
PGR(7:0)
Rdy/Bsy
16
3
1
1
8
8
8
4
8
8
1
Table 12. DPLD and GPLD Inputs
NOTE:
The address inputs are A[19:4] in 80C51XA mode.
The Turbo Bit
The PLDs in the PSD935G2 can minimize power consumption by switching to standby
when inputs remain unchanged for an extended time of about 70 ns. Setting the Turbo
mode bit to off (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if
no inputs are changing. Turbo-off mode increases propagation delays while reducing
power consumption. Refer to the Power Management Unit section on how to set the Turbo
Bit. Additionally, five bits are available in the PMMR2 register to block MCU control signals
from entering the PLDs. This reduces power consumption and can be used only when
these MCU control signals are not used in PLD logic equations.
相關(guān)PDF資料
PDF描述
PSD935F3V-15B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15B81I Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 30000uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-0.1pF; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder Coated (Sn/Pb, 70/30); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate
PSD935F3V-15J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15M Configurable Memory System on a Chip for 8-Bit Microcontrollers
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