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參數(shù)資料
| 型號： | FMS9874AKGC100 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 454K |
| 代理商： | FMS9874AKGC100 |
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FMS9874A
PRODUCT SPECIFICATION
REV. 1.2.10 1/14/02
15
Figure 17.
50% Timeout
HSIN
COAST
HSOUT
Trailing edge terminates HSOUT
Timing Generator
Timing and Control logic generates:
1.
Internal sampling clock, SCK.
2.
Output data clocks, DCK and DCK.
3.
Output horizontal sync, HSOUT.
4.
Internal clamp pulse, ICLAMP.
With HSPOL set correctly, ICLAMP delay follows the trail-
ing edge of horizontal sync in (HSIN). Delay is set by the
CD register. Width of ICLAMP is set by the CW register.
Range of CD and CW values is 1–255 pixels.
Sync Stripper
Some video signals include embedded composite sync rather
than separate horizontal and vertical sync signals, typically
sync on green. Composite sync is extracted from Composite
Video at the ACSIN pin.
When the ACSIN signal falls below a 150mV ground refer-
enced threshold, sync is detected. Composite Sync Output,
DCSOUT reects the ACSIN sync timing with non-inverted
CMOS digital levels.
Power Down
PWRDN = L minimizes FMS9874A power consumption.
Data outputs become high impedance. Clocks generation is
stopped. Register contents are retained. Sync stripping and
the internal voltage reference function.
Serial Interface
Register access is via a 2-wire I2C/SMBus compatible inter-
face. As a slave device, the 7-bit address is selected by the
A1-0 pins (see Table 7). Serial port pins SDA and SCL com-
municate with the host SMBus/I2C controller which act as a
master.
Since the serial control port is design to interface with 3.3V
logic, the pins must be protected, if SDA and SCL signals
originate from 5V logic. Series connected 150
resistors are
recommended. (See Applications Section)
Table 7. Serial Interface Address Codes
Two signals comprise the bus: clock (SCL) and bi-directional
data (SDA). When receiving and transmitting data through
the serial interface, the FMS9874A acts as a slave, responding
only to commands by the I2C/SMBus master.
Data received or transmitted on the SDA line must be stable
for the duration of the positive-going SCL pulse. Data on
SDA may change only when SCL = L. An SDA transition
while SCL = H is interpreted as a start or stop signal.
A1-0
7-Bit Address
00
4C
01
4D
10
4E
11
4F
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FMS9874KGC | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| FMS9874KGC100 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Graphics Digitizer - 3x8-Bit, 108Ms/s Triple Video A/D Converter with Clamps |
| FMS9875 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL |
| FMS9875KAC100 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL |
| FMS9875KAC140 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL |
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