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參數(shù)資料
| 型號： | FMS9874AKGC100 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 21/26頁 |
| 文件大?。?/td> | 454K |
| 代理商： | FMS9874AKGC100 |
PRODUCT SPECIFICATION
FMS9874A
4
REV. 1.2.10 1/14/02
Pin Descriptions
Pin Name
Pin No.
Type/Value
Pin Function Description
Converter Channels
RIN, GIN, BIN
2, 8, 13
Input
Analog Inputs.
DR7-0
76–83
Output
Red Channel A Data Output.
DG7-0
63–70
Output
Green Channel A Data Output.
DB7-0
51–58
Output
Blue Channel A Data Output.
Timing Generator
CLAMP
19
Input
External Clamp Input.
INVSCK
18
Input
Invert Sampling Clock. Inverts SCK, the internal clock sampling the
analog inputs. Supports Alternate Pixel Sampling mode for capture
pixel rates up to 216Ms/s.
XCK
32
Input
External Clock input. Enabled if register bit, XCKSEL = H. Replaces
PXCK clock generated by PLL. If unused, connect to ground through a
10k
resistor.
DCK
86
Output
Output Data Clock. Clock for strobing output data to external logic.
DCK
87
Output
Output Data Clock Inverted. Inverted clock for strobing output data to
external logic.
HSOUT
88
Output
Horizontal Sync Output. Reconstructed HSYNC delayed by
FMS9874A latency. Leading edge is synchronized to start of data
output. Polarity is always active HIGH.
Phase Locked Loop
HSIN
28
Schmitt
Horizontal Sync input. Schmitt trigger threshold is 1.5V. A 5V source
should be clamped at 3.3V or current limited, to prevent overdriving
ESD protection diodes.
COAST
29
Input
PLL COAST. Extraneous or missing horizontal sync pulses can be
ignored by asserting the COAST input. With COAST asserted, the HSIN
signal is ignored by the PLL without affecting PXCK and the derived
clocks: SCK, DCK and DCK. With register bit, COASTPOL = 1:
COAST = L: PLL locked to HSIN.
COAST = H: PLL VCO input floats with HSIN disregarded
COAST polarity may be inverted using the COASTPOL register bit.
LPF
33
Passive
PLL Low Pass Filter. Connect recommended PLL filter to LPF pin.
(see Schematic, PLL Filter.)
Sync Stripper
ACSIN
7
Analog Composite Sync Input. Input to sync stripper with 150mV
threshold.
DCSOUT
89
Digital Composite Sync Output. Output from sync stripper.
Control
SDA
20
Bi-directional Serial Port Data. Bi-directional data (I2C/SMBUS).
SCL
21
Input
Serial Port Clock. Clock input (I2C/SMBUS).
A0
22
Input
Address bit 0. Lower bit of serial port address.
A1
23
Input
Address bit 1. Upper bit of serial port address.
PWRDN
96
Input
Power Down/Output Control. Powers down the FMS9874A with
outputs high impedance.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| FMS9874KGC | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| FMS9874KGC100 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Graphics Digitizer - 3x8-Bit, 108Ms/s Triple Video A/D Converter with Clamps |
| FMS9875 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL |
| FMS9875KAC100 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL |
| FMS9875KAC140 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL |
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