參數(shù)資料
型號： FMS9874AKGC100
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： ADC
英文描述： 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100
封裝： MQFP-100
文件頁數(shù)： 5/26頁
文件大?。?/td> 454K
代理商： FMS9874AKGC100
FMS9874A
PRODUCT SPECIFICATION
REV. 1.2.10 1/14/02
13
Timing and Control
Timing and Control logic encompasses the PLL, Timing
Generator and Sync Stripper.
Phase Locked Loop
Two clock types originate in the PLL:
1.
Data clocks DCK and DCK.
2.
Internal sampling clock SCK.
DCK and DCK are used to strobe data from the FMS9874A
to following digital circuits. SCK is the ADC sample clock
which has adjustable phase controlled through the PHASE
register. DCK and DCK are phase aligned with SCK.
Reference for the PLL is the horizontal sync input, HSIN
with polarity selected by the HSPOL bit.
Frequency of the HSIN input is multiplied by the value PLLN
+ 1 derived from the PLLN11-4 and PLLN3-0 registers. PLLN
+ 1 should equal the number of pixels per horizontal line
including active and blanked sections. Typically blanking is
20–30% of active pixels. Divide ratios from 2–4095 are
supported. SCK, DCK and DCK run at a rate PLLN + 1
times the HSIN frequency.
The PLL consists of a phase comparator, charge pump VCO
and
÷N counter, with the charge pump connected through the
LPF pin to an external lter. These elements must be pro-
grammed to match the incoming video source to be captured.
Values of IPUMP and FVCO for Standard VESA timing
parameters are shown in Table 4. Timing of many computer
video outputs does not comply with VESA recommendations.
PLLN should be optimized to avoid vertical noise bars on the
displayed image.
HSIN
/N
i
o
Phase
Detector
Charge
Pump
VCO
KV
Sub-
divider
SCK
(DCK)
IP
C1
C2
VZ
VDDP
Divider
Θ
o
Θ
R
O1
E2
O1
E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
Figure 13. Even Pixels from Frame 2
Figure 14. Subsequent Output
Figure 15. Combined Frames
Combining Frames 2 and 3
2 and 3
Notes:
1. VESA Monitor Timing Standards and Guidelines, September 17, 1998 and others.
2. VCO runs at 2x sample rate when SUBDIV1-0 = 2.
Table 4. Recommended IPUMP and FVCO values for Standard Display Formats1
Standard
Test
Rank
Resolution
Refresh
Rate
Horizontal
Frequency
Sample Rate FVCO1-0
IPUMP2-0 SUBDIV1-0
VGA
C
640 X 480
60 Hz
75 Hz
85 Hz
31.5 kHz
37.5 kHz
43.3 kHz
25.175 MHz
31.500 MHz
36.000 MHz
01
110
2
SVGA
C
CT
800 X 600
60 Hz
75 Hz
85 Hz
37.9 kHz
46.9 kHz
53.7 kHz
40.000 MHz
49.500 MHz
56.250 MHz
01
110
1
XGA
C
1024 X 768
60 Hz
75 Hz
85 Hz
48.4 kHz
60.0 kHz
68.3 kHz
65.000 MHz
78.750 MHz
94.500 MHz
10
11
110
1
SXGA
C
CT
1280 X 1024
60 Hz
72 Hz
75 Hz
64.0 kHz
78.1 kHz
80.0 kHz
108.000 MHz
135.000 MHz
11
110
111
1
相關(guān)PDF資料
PDF描述
FMS9874AKGC140 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100
FMS9875KGC100 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100
FMS9875KGC100X 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100
FMS9875KGC140 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100
FMS9875KGC140X 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FMS9874KGC 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
FMS9874KGC100 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Graphics Digitizer - 3x8-Bit, 108Ms/s Triple Video A/D Converter with Clamps
FMS9875 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL
FMS9875KAC100 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL
FMS9875KAC140 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL
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