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參數(shù)資料
| 型號： | FMS9874AKGC100 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 23/26頁 |
| 文件大?。?/td> | 454K |
| 代理商： | FMS9874AKGC100 |
PRODUCT SPECIFICATION
FMS9874A
6
REV. 1.2.10 1/14/02
Register Denitions
PLLCTRL
0C
PLL Control
24
CONFIG 2
0D
Configuration Register No. 2
00
0E
Reserved
00
0F
Reserved
00
PLL Control Register (01)
Bit no.
Name
Type
Description
1-0
SUBDIV1-0
R/W
PLL Subdivide ratio. Selects the ratio of the divider following the PLL.
00: divide-by 1
01: divide-by 2
10: divide-by 4
11: Reserved
2
PLLFAZ
R/W
PLL Sub-divider Phase. Selects the phase of the divide-by-2 output.
(Invalid for other outputs)
3
–
R/W
Reserved.
7-4
PLLN3-0
R/W
PLL divide ratio, LSBs. PLLN + 1 = total number of pixels per horizontal line.
Conguration Register 1 (0A)
Bit no.
Name
Type
Description
0
1
XCKSEL
R/W
External Clock Select. Select internal clock source.
0: Internal PLL
1: XCK input.
2
XCLAMPOL
R/W
External Clamp Polarity. Select clamp polarity.
0: Active L.
1: Active H.
3
XCLAMP
R/W
External Clamp Select. Select clamp source.
0: Internally generated by PLL referenced to HSIN.
1: External CLAMP input.
4
COASTPOL
R/W
Coast Polarity. Select COAST input polarity.
0: Active L.
1: Active H.
5
HSPOL
R/W
HSIN Polarity. Select horizontal sync input polarity. PLL is locked to selected
edge:
0: Falling edge.
1: Rising edge.
6—
R
1
7—
R
1
Name
Address
Function
Default (hex)
PLLSUB1–0
XXXX
PLLN3–0
X X X
X
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