參數(shù)資料
型號(hào): FMS9874AKGC100
廠(chǎng)商: FAIRCHILD SEMICONDUCTOR CORP
元件分類(lèi): ADC
英文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100
封裝: MQFP-100
文件頁(yè)數(shù): 25/26頁(yè)
文件大?。?/td> 454K
代理商: FMS9874AKGC100
PRODUCT SPECIFICATION
FMS9874A
8
REV. 1.2.10 1/14/02
Functional Description
There are two major sections within the FMS9874A:
1.
Analog-to-digital Converter Channels, one for each
channel, RGB and the voltage reference.
2.
Timing and Control comprising the PLL, Timing
Generator, Sync Stripper and Serial Interface.
A/D Converter Channels
Each of the three RGB channels consists of:
1.
A clamp to set the lower reference level of an AC
coupled input.
2.
Gain and offset stages to match the A/D converter range
to input signal levels.
3.
An Analog-to-Digital Converter to digitize the analog
input.
A Plot of output codes versus input voltage has a staircase-
like shape. With FMS 9874A Gain and Offset register values
trimmed to match a 700 mV input, Table 1 shows the output
codes corresponding to the mid-point input voltages of each
step. Note:
1.
The midpoint of code 000 lies 1/2 of one code-size
below the 000/001 transition.
2.
The midpoint of code 255 lies 1/2 of one code-size
above the 254/255 transition.
3.
AC coupled input is clamped to FMS9875A bottom
reference, during the blanking period.
Table 1. RGB Output Coding
Analog Inputs
Input signal range is 500 to 1000mV to support conversion of
single-ended signals with a typical amplitude of 700mV p-p.
With the clamp active, each input can accommodate com-
posite sync, a negative 300mV excursion.
Inputs are optimized for a source resistance of 37.5 to 75
.
To reduce noise sensitivity, the 400MHz input bandwidth
may be reduced by adding a small series inductor capacitor
across each RGB input. See Applications Section.
Clamps
If the incoming signals are not ground referenced, a clamp
must be used to establish the incoming video range relative
to ground. Prior to each A/D converter, each channel
includes a clamp that allows a capacitively coupled input to be
referenced to the A/D converter bottom reference voltage
when the clamp pulse is active. Source of the clamp signal is
determined by the XCLAMP register bit.
Internal clamp timing is generated by the Timing and Con-
trol Block. Position and width of the internal clamp pulse,
ICLAMP are programmable through registers CD and CW.
External clamp input is selected by register bit XCLAMP
and the external clamp polarity selected through register bit
XCLAMPOL. To disable the clamp for DC coupled inputs,
set XCLAMP = 1 with either of these conditions:
1.
XCLAMPOL = 0 with input CLAMP = H.
2.
XCLAMPOL = 1 with input CLAMP = L.
Best performance will be achieved with the clamp set active
for most of the black signal level interval between the trailing
edge of horizontal sync and the start of active video. Insufcient
clamping can cause brightness changes at the top of the image
and slow recovery from large changes in Average Picture
Level (APL). Recommended clamp delay value, CD is 0x10
to 0x20 for most standard video sources.
Input (mV)
Decimal
Binary
700
255
1111 1111
697.25
254
1111 1110
351.37
128
1000 0000
348.63
127
0111 1111
345.88
126
0111 1110
2.75
001
0000 0001
0
000
0000 0000
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FMS9874KGC 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
FMS9874KGC100 制造商:FAIRCHILD 制造商全稱(chēng):Fairchild Semiconductor 功能描述:Graphics Digitizer - 3x8-Bit, 108Ms/s Triple Video A/D Converter with Clamps
FMS9875 制造商:FAIRCHILD 制造商全稱(chēng):Fairchild Semiconductor 功能描述:Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL
FMS9875KAC100 制造商:FAIRCHILD 制造商全稱(chēng):Fairchild Semiconductor 功能描述:Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL
FMS9875KAC140 制造商:FAIRCHILD 制造商全稱(chēng):Fairchild Semiconductor 功能描述:Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL