參數(shù)資料
型號： FLEX10K
廠商： Altera Corporation
英文描述： Embedded Programmable Logic Family
中文描述： 嵌入式可編程邏輯系列
文件頁數(shù)： 97/114頁
文件大?。?/td> 1422K
代理商： FLEX10K
Altera Corporation
97
FLEX 10K Embedded Programmable Logic Family Data Sheet
Notes:
(1)
To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the
input frequency. The MAX+PLUS II software tunes the PLL in the ClockLock and ClockBoost circuitry to this
frequency. The
f
CLKDEV
parameter specifies how much the incoming clock can differ from the specified frequency
during device operation. Simulation does not reflect this parameter.
During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration, because the
t
LOCK
value
is less than the time required for configuration.
The
t
JITTER
specification is measured under long-term observation.
Power
Consumption
P = P
INT
+ P
IO
= (I
CC
STANDBY
+ I
CCACTIVE
)
×
V
CC
+ P
IO
(2)
(3)
The supply power (P) for FLEX 10K devices can be calculated with the
following equation:
Typical I
CC
values are shown as I
CC0
in the òFLEX 10K 5.0-V
Device DC Operating Conditionsó table on pages 41, 44, and 46 of this
data sheet. The I
CCACTIVE
value depends on the switching frequency and
the application logic. This value is calculated based on the amount of
current that each LE typically consumes. The P
IO
value, which depends
on the device output load characteristics and switching frequency, can be
calculated using the guidelines given in
Application Note 74 (Evaluating
Power for Altera Devices)
in this data book.
Table 21. ClockLock & ClockBoost Parameters (Part 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
t
R
t
F
t
INDUTY
f
CLK1
t
CLK1
f
CLK2
t
CLK2
f
CLKDEV1
Input rise time
2
ns
Input fall time
2
ns
%
Input duty cycle
45
55
Input clock frequency (ClockBoost clock multiplication factor equals 1)
30
80
MHz
Input clock period (ClockBoost clock multiplication factor equals 1)
12.5
33.3
ns
Input clock frequency (ClockBoost clock multiplication factor equals 2)
16
50
MHz
Input clock period (ClockBoost clock multiplication factor equals 2)
20
62.5
±
1
ns
Input deviation from user specification in MAX+PLUS II, (ClockBoost clock
multiplication factor equals 1), Note (1)
MHz
f
CLKDEV2
Input deviation from user specification in MAX+PLUS II, (ClockBoost clock
multiplication factor equals 2), Note (1)
±
0.5
MHz
t
INCLKSTB
Input clock stability (measured between adjacent clocks)
100
ps
Table 21. ClockLock & ClockBoost Parameters (Part 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
t
LOCK
t
JITTER
t
OUTDUTY
Duty cycle for ClockLock or ClockBoost-generated clock
Time required for ClockLock or ClockBoost to acquire lock, Note (2)
10
μ
s
ns
Jitter on ClockLock or ClockBoost-generated clock, Note (3)
1
40
50
60
%
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