參數(shù)資料
型號(hào): FLEX10K
廠商: Altera Corporation
英文描述: Embedded Programmable Logic Family
中文描述: 嵌入式可編程邏輯系列
文件頁數(shù): 96/114頁
文件大?。?/td> 1422K
代理商: FLEX10K
96
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Note:
(1)
These timing parameters are preliminary. For the most up-to-date information, contact Altera Applications at
(800) 800-EPLD.
ClockLock &
ClockBoost
Timing
Parameters
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock during configuration. The circuit will be ready for use immediately
after configuration. Figure 28 illustrates the incoming and generated clock
specifications.
Figure 28. Specifications for the Incoming & Generated Clocks
The t
I
parameter refers to the nominal input clock period; the t
O
parameter refers to the
nominal output clock period.
Table 21 summarizes the ClockLock and ClockBoost parameters.
External Reference Timing Parameters
Note (1)
Symbol
Device
-1 Speed Grade
Min
-2 Speed Grade
Min
-3 Speed Grade
Min
Unit
Max
Max
Max
t
DRR
EPF10K10A
EPF10K30A
EPF10K100B
EPF10K250A
10.0
11.0
10.5
14.5
12.0
14.0
12.0
16.5
16.0
17.0
13.5
19.0
ns
ns
ns
ns
t
R
t
F
t
CLK1
t
INDUTY
t
I
±
f
CLKDEV
t
I
t
I
±
t
INCLKSTB
t
OUTDUTY
t
O
t
O +
t
JITTER
t
O –
t
JITTER
Input
Clock
ClockLock-
Generated
Clock
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