參數(shù)資料
型號(hào)： FLEX10K
廠商： Altera Corporation
英文描述： Embedded Programmable Logic Family
中文描述： 嵌入式可編程邏輯系列
文件頁數(shù)： 20/114頁
文件大小： 1422K
代理商： FLEX10K
20
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Normal Mode
The normal mode is suitable for general logic applications and wide
decoding functions that can take advantage of a cascade chain. In normal
mode, four data inputs from the LAB local interconnect and the carry-in
are inputs to a 4-input LUT. The MAX+PLUS II Compiler automatically
selects the carry-in or the
DATA3
signal as one of the inputs to the LUT. The
LUT output can be combined with the cascade-in signal to form a cascade
chain through the cascade-out signal. Either the register or the LUT can be
used to drive both the local interconnect and the FastTrack Interconnect at
the same time.
The LUT and the register in the LE can be used independently; this feature
is known as register packing. To support register packing, the LE has two
outputs; one drives the local interconnect and the other drives the
FastTrack Interconnect. The
DATA4
signal can drive the register directly,
allowing the LUT to compute a function that is independent of the
registered signal; a 3-input function can be computed in the LUT, and a
fourth independent signal can be registered. Alternatively, a 4-input
function can be generated, and one of the inputs to this function can be
used to drive the register. The register in a packed LE can still use the
clock enable, clear, and preset signals in the LE. In a packed LE, the
register can drive the FastTrack Interconnect while the LUT drives the
local interconnect, or vice versa.
Arithmetic Mode
The arithmetic mode offers two 3-input LUTs that are ideal for
implementing adders, accumulators, and comparators. One LUT
computes a 3-input function; the other generates a carry output. As shown
in Figure 9 on page 19, the first LUT uses the carry-in signal and two data
inputs from the LAB local interconnect to generate a combinatorial or
registered output. For example, in an adder, this output is the sum of three
signals:
a
,
b
, and carry-in. The second LUT uses the same three signals to
generate a carry-out signal, thereby creating a carry chain. The arithmetic
mode also supports simultaneous use of the cascade chain.
Up/Down Counter Mode
The up/down counter mode offers counter enable, clock enable,
synchronous up/down control, and data loading options. These control
signals are generated by the data inputs from the LAB local interconnect,
the carry-in signal, and output feedback from the programmable register.
Two 3-input LUTs are used: one generates the counter data, and the other
generates the fast carry bit. A 2-to-1 multiplexer provides synchronous
loading. Data can also be loaded asynchronously with the clear and preset
register control signals, without using the LUT resources.
相關(guān)PDF資料
PDF描述
FLEX10KA Embedded Programmable Logic Family
FLEX10KE Embedded Programmable Logic Family
FLEX6000 Programmable Logic Device Family
FLEX8000 PROGRAMMABLE LOGIC DEVICES FAMILY
FLL120MK L-Band Medium & High Power GaAs FET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FLEX10K_03 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Embedded Programmable Logic Device Family
FLEX10KA 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Embedded Programmable Logic Family
FLEX10KE 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Embedded Programmable Logic Device
FLEX110 功能描述:開發(fā)板和工具包 - PIC / DSPIC Multibus Pack RoHS:否 制造商:Microchip Technology 產(chǎn)品:Starter Kits 工具用于評(píng)估:chipKIT 核心:Uno32 接口類型: 工作電源電壓:
FLEX111 功能描述:開發(fā)板和工具包 - PIC / DSPIC Fasttrack suite RoHS:否 制造商:Microchip Technology 產(chǎn)品:Starter Kits 工具用于評(píng)估:chipKIT 核心:Uno32 接口類型: 工作電源電壓:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*