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參數(shù)資料
| 型號： | FLEX10K |
| 廠商： | Altera Corporation |
| 英文描述： | Embedded Programmable Logic Family |
| 中文描述： | 嵌入式可編程邏輯系列 |
| 文件頁數(shù)： | 23/114頁 |
| 文件大?。?/td> | 1422K |
| 代理商： | FLEX10K |
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Altera Corporation
23
FLEX 10K Embedded Programmable Logic Family Data Sheet
Asynchronous Clear
The flipflop can be cleared by either
LABCTRL1
or
LABCTRL2
. In this mode,
the preset signal is tied to
VCC
to deactivate it.
Asynchronous Preset
An asynchronous preset is implemented as either an asynchronous load,
or with an asynchronous clear. If
DATA3
is tied to
VCC
, asserting
LABCTRL1
asynchronously loads a one into the register. Alternatively, the
MAX+PLUS II software can provide preset control by using the clear and
inverting the input and output of the register. Inversion control is
available for the inputs to both LEs and IOEs. Therefore, if a register is
preset by only one of the two
LABCTRL
signals, the
DATA3
input is not
needed and can be used for one of the LE operating modes.
Asynchronous Preset & Clear
When implementing asynchronous clear and preset,
LABCTRL1
controls
the preset and
LABCTRL2
controls the clear.
DATA3
is tied to
VCC
, therefore,
asserting
LABCTRL1
asynchronously loads a one into the register,
effectively presetting the register. Asserting
LABCTRL2
clears the register.
Asynchronous Load with Clear
When implementing an asynchronous load in conjunction with the clear,
LABCTRL1
implements the asynchronous load of
DATA3
by controlling the
register preset and clear.
LABCTRL2
implements the clear by controlling
the register clear;
LABCTRL2
does not have to feed the preset circuits.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with preset, the
MAX+PLUS II software provides preset control by using the clear and
inverting the input and output of the register. Asserting
LABCTRL2
presets
the register, while asserting
LABCTRL1
loads the register. The
MAX+PLUS II software inverts the signal that drives
DATA3
to account for
the inversion of the registers output.
Asynchronous Load without Preset or Clear
When implementing an asynchronous load without preset or clear,
LABCTRL1
implements the asynchronous load of
DATA3
by controlling the
register preset and clear.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| FLEX10K_03 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Embedded Programmable Logic Device Family |
| FLEX10KA | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Embedded Programmable Logic Family |
| FLEX10KE | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Embedded Programmable Logic Device |
| FLEX110 | 功能描述:開發(fā)板和工具包 - PIC / DSPIC Multibus Pack RoHS:否 制造商:Microchip Technology 產品:Starter Kits 工具用于評估:chipKIT 核心:Uno32 接口類型: 工作電源電壓: |
| FLEX111 | 功能描述:開發(fā)板和工具包 - PIC / DSPIC Fasttrack suite RoHS:否 制造商:Microchip Technology 產品:Starter Kits 工具用于評估:chipKIT 核心:Uno32 接口類型: 工作電源電壓: |
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