參數(shù)資料
型號(hào): FLEX10K
廠商: Altera Corporation
英文描述: Embedded Programmable Logic Family
中文描述: 嵌入式可編程邏輯系列
文件頁數(shù): 28/114頁
文件大?。?/td> 1422K
代理商: FLEX10K
28
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
I/O Element
An I/O element (IOE) contains a bidirectional I/O buffer and a register
that can be used either as an input register for external data that requires
a fast setup time, or as an output register for data that requires fast clock-
to-output performance. In some cases, using an LE register for an input
register will result in a faster setup time than using an IOE register. IOEs
can be used as input, output, or bidirectional pins. The MAX+PLUS II
Compiler uses the programmable inversion option to invert signals from
the row and column interconnect automatically where appropriate.
Figure 13 shows the IOE block diagram.
Figure 13. I/O Element
VCC
from Row or Column
Interconnect
to Row or Column
Interconnect
OE[7..0]
CLK[1..0]
ENA[5..0]
CLRn[1..0]
Peripheral Control
Bus
CLRN
D
Q
ENA
VCC
2 Dedicated
Clock Inputs
Slew-Rate
Control
Open-Drain
Output
Chip-Wide
Output Enable
CLK[3..2]
from One Row or
Column Channel
2
12
VCC
VCC
Chip-Wide
Reset
from One Row or
Column Channel
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